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arch: arm: Set Zero Latency IRQ to priority level zero: #8109

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joerchan
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@joerchan joerchan commented Jun 1, 2018

Set Zero Latency IRQ to priority level zero and SVCs to priority level
one when Zero Latency IRQ is enabled.
This makes Zero Zatency truly zero latency when the kernel has been
configured with userspace enabled, or when IRQ offloading is used.

Exceptions can still delay Zero Latency IRQ, but this is considered
ok since exceptions indicate a serious error, and the system needs to
recover.

Fixes: #7869

@joerchan
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joerchan commented Jun 1, 2018

FYI: @carlescufi @ioannisg @andrewboie

@ioannisg ioannisg added the area: ARM ARM (32-bit) Architecture label Jun 1, 2018
@ioannisg ioannisg added this to the v1.13.0 milestone Jun 1, 2018
@ioannisg ioannisg requested a review from agross-oss June 1, 2018 11:15
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codecov-io commented Jun 1, 2018

Codecov Report

Merging #8109 into master will not change coverage.
The diff coverage is n/a.

Impacted file tree graph

@@           Coverage Diff           @@
##           master    #8109   +/-   ##
=======================================
  Coverage   64.54%   64.54%           
=======================================
  Files         420      420           
  Lines       40142    40142           
  Branches     6765     6765           
=======================================
  Hits        25911    25911           
  Misses      11110    11110           
  Partials     3121     3121

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@ioannisg
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ioannisg commented Jun 1, 2018

Are there any implications from SVC being blocked by zero-latency peripheral IRQs?

I agree that Fault exceptions having highest priority (equal to zero-latency) is OK.

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@ioannisg I can't think of any. You'd have to invoke an SVC in the zero latency peripheral IRQ to run into issues, which I don't see happening. And if the SVC is interrupted, it should still pick up where it left off without any issue.

Zero-latency interrupt can be used to set up an interrupt at the
highest interrupt priority which will not be blocked by interrupt
locking.
Since Zero-latency ISRs will run in the same priority or possible at
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possibly

#define _EXC_FAULT_PRIO 0
#ifdef CONFIG_ZERO_LATENCY_IRQS
#define _EXC_ZERO_LATENCY_IRQS_PRIO 1
#define _EXC_SVC_PRIO 1
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Thinking aloud, should SVC be masked? Why ZLI at same priority as SVC?
is the below correct?
#define _EXC_SVC_PRIO _EXCEPTION_RESERVED_PRIO
#ifdef CONFIG_ZERO_LATENCY_IRQS
#define _EXC_ZERO_LATENCY_IRQS_PRIO _EXC_SVC_PRIO
#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + 1)
#else
#define _IRQ_PRIO_OFFSET _EXCEPTION_RESERVED_PRIO
#endif

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I don't think SVCs should be masked, they weren't before, and shouldn't be now.
ZLI at the same priority as SVC, I messed up in the rebase here, it should be 0.

Set Zero Latency IRQ to priority level zero and SVCs to priority level
one when Zero Latency IRQ is enabled.
This makes Zero Zatency truly zero latency when the kernel has been
configured with userspace enabled, or when IRQ offloading is used.

Exceptions can still delay Zero Latency IRQ, but this is considered
ok since exceptions indicate a serious error, and the system needs to
recover.

Fixes: zephyrproject-rtos#7869

Signed-off-by: Joakim Andersson <[email protected]>
@joerchan joerchan force-pushed the zero_latency_interrupts_prio_zero branch from 0f2e2cf to 6becaf8 Compare June 5, 2018 12:20
@carlescufi
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@cvinayak can you revisit? This looks good to me but I'd like someone else to take a look.
@agross-linaro, @andrewboie, @andyross any comments on this one?

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LGTM

@carlescufi
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@agross-linaro @andrewboie @andyross Can you please take a look at this?

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I'm not expert enough on ARM Cortex priority handling to review the design, but the logic looks correct and the documentation and justification are clear.

@carlescufi carlescufi merged commit 5204fd7 into zephyrproject-rtos:master Jun 20, 2018
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@andyross thank you

@joerchan joerchan deleted the zero_latency_interrupts_prio_zero branch September 24, 2019 11:38
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7 participants