Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add Verilog files for FPGA/Misc/PTMClock package #18

Merged
merged 1 commit into from
Aug 22, 2021
Merged

Add Verilog files for FPGA/Misc/PTMClock package #18

merged 1 commit into from
Aug 22, 2021

Conversation

quark17
Copy link
Collaborator

@quark17 quark17 commented Aug 22, 2021

The PTMClock package imports two Verilog modules that were still in the BSC repo and had accidentally not been migrated here. (They were removed from the BSC repo in B-Lang-org/bsc#388.)

This repo had not yet been installing any Verilog files, and I had to add a mechanism for storing and installing them. The current structure of this repo mirrors what the BSC repo does, where the library sources are in one (possibly interdependent) tree and the Verilog is in a separate tree. I would prefer that this repo be structured by project, keeping the source and Verilog (and docs and scripts and any other files) together. But for now I've just continued to mirror what the BSC repo does.

@quark17 quark17 merged commit d2b17aa into B-Lang-org:main Aug 22, 2021
@quark17 quark17 deleted the add-verilog-prims branch August 22, 2021 23:15
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant