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Remove old Verilog prims / ifdefs #388

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merged 2 commits into from
Jul 29, 2021

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@quark17 quark17 commented Jul 29, 2021

Apply the first two commits from PR #295 while deciding when to apply the third

Icarus seems to support the 'generate' constructs used here for BRAMs,
so there's no need to use this workaround anymore.

Signed-off-by: Austin Seipp <[email protected]>
@quark17 quark17 merged commit ae7084d into B-Lang-org:main Jul 29, 2021
@quark17 quark17 deleted the aseipp-verilog-cleanups branch July 29, 2021 03:38
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