Update docs, index new specs, and add eTRNG disclaimer (#155)

* Link the HW integration spec explicitly

* Index the HW integration spec

* Add eTRNG disclaimer

* RNG -> TRNG language fix

README.md

@@ -26,6 +26,8 @@ marks](https:/chipsalliance/Caliptra/blob/main/CaliptraTrademarkPoli
 ## Specifications
 
 * [Main Caliptra specification](https:/chipsalliance/Caliptra/blob/main/doc/Caliptra.md)
+* [Hardware Integration
+ Specification](https:/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md)
 * [ROM](https:/chipsalliance/caliptra-sw/blob/main/rom/dev/README.md)
 * [FMC](https:/chipsalliance/caliptra-sw/blob/main/fmc/README.md)
 * [Firmware](https:/chipsalliance/caliptra-sw/blob/main/runtime/README.md)

doc/Caliptra.md

@@ -1060,8 +1060,8 @@ The following figure describes the Caliptra Core.
 * Chips Alliance is used for RISC-V.
 * APB is the choice for the SoC-facing interface.
 * JTAG is exported at the IP interface.
-* TRNG is the digital logic and algorithms that are required for random number generation. It requires a physical entropy source input. See the Caliptra IP specification and integration specification for more information.
- * For SoCs that want to use their own legacy TRNG, Caliptra provides a HW API to push the random number on the request/response handshake. See the Caliptra IP specification and integration specification for more information.
+* TRNG is the digital logic and algorithms that are required for random number generation. It requires a physical entropy source input. See the Caliptra IP specification and [integration specification](https:/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md) for more information.
+ * For SoCs that want to use their own legacy TRNG, Caliptra provides a HW API to push the random number on the request/response handshake. See the Caliptra IP specification and [integration specification](https:/chipsalliance/caliptra-rtl/blob/main/docs/CaliptraIntegrationSpecification.md) for more information. **This mode is advised for early development but discouraged for production tape outs due to the lower security assurances of an external TRNG**.
 
 The following figure describes the Caliptra IP HW boot flow.