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Revert reg files
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Kiran Upadhyayula committed Sep 11, 2024
1 parent 3353284 commit 27503eb
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Showing 13 changed files with 1,974 additions and 1,003 deletions.
58 changes: 38 additions & 20 deletions src/datavault/rtl/dv_reg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -235,8 +235,10 @@ module dv_reg (
for(genvar i0=0; i0<10; i0++) begin
// Field: dv_reg.StickyDataVaultCtrl[].lock_entry
always_comb begin
automatic logic [0:0] next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value;
automatic logic load_next_c = '0;
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value;
load_next_c = '0;
if(decoded_reg_strb.StickyDataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyDataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
next_c = (field_storage.StickyDataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
Expand All @@ -257,8 +259,10 @@ module dv_reg (
for(genvar i1=0; i1<12; i1++) begin
// Field: dv_reg.STICKY_DATA_VAULT_ENTRY[][].data
always_comb begin
automatic logic [31:0] next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value;
automatic logic load_next_c = '0;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value;
load_next_c = '0;
if(decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.STICKY_DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
next_c = (field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
Expand All @@ -278,8 +282,10 @@ module dv_reg (
for(genvar i0=0; i0<10; i0++) begin
// Field: dv_reg.DataVaultCtrl[].lock_entry
always_comb begin
automatic logic [0:0] next_c = field_storage.DataVaultCtrl[i0].lock_entry.value;
automatic logic load_next_c = '0;
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.DataVaultCtrl[i0].lock_entry.value;
load_next_c = '0;
if(decoded_reg_strb.DataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.DataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
next_c = (field_storage.DataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
Expand All @@ -300,8 +306,10 @@ module dv_reg (
for(genvar i1=0; i1<12; i1++) begin
// Field: dv_reg.DATA_VAULT_ENTRY[][].data
always_comb begin
automatic logic [31:0] next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value;
automatic logic load_next_c = '0;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value;
load_next_c = '0;
if(decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
next_c = (field_storage.DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
Expand All @@ -321,8 +329,10 @@ module dv_reg (
for(genvar i0=0; i0<10; i0++) begin
// Field: dv_reg.LockableScratchRegCtrl[].lock_entry
always_comb begin
automatic logic [0:0] next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
automatic logic load_next_c = '0;
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
load_next_c = '0;
if(decoded_reg_strb.LockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
next_c = (field_storage.LockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
Expand All @@ -342,8 +352,10 @@ module dv_reg (
for(genvar i0=0; i0<10; i0++) begin
// Field: dv_reg.LockableScratchReg[].data
always_comb begin
automatic logic [31:0] next_c = field_storage.LockableScratchReg[i0].data.value;
automatic logic load_next_c = '0;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.LockableScratchReg[i0].data.value;
load_next_c = '0;
if(decoded_reg_strb.LockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchReg[i0].data.swwel)) begin // SW write
next_c = (field_storage.LockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
Expand All @@ -362,8 +374,10 @@ module dv_reg (
for(genvar i0=0; i0<8; i0++) begin
// Field: dv_reg.NonStickyGenericScratchReg[].data
always_comb begin
automatic logic [31:0] next_c = field_storage.NonStickyGenericScratchReg[i0].data.value;
automatic logic load_next_c = '0;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.NonStickyGenericScratchReg[i0].data.value;
load_next_c = '0;
if(decoded_reg_strb.NonStickyGenericScratchReg[i0] && decoded_req_is_wr) begin // SW write
next_c = (field_storage.NonStickyGenericScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
Expand All @@ -382,8 +396,10 @@ module dv_reg (
for(genvar i0=0; i0<8; i0++) begin
// Field: dv_reg.StickyLockableScratchRegCtrl[].lock_entry
always_comb begin
automatic logic [0:0] next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value;
automatic logic load_next_c = '0;
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value;
load_next_c = '0;
if(decoded_reg_strb.StickyLockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
next_c = (field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
Expand All @@ -403,8 +419,10 @@ module dv_reg (
for(genvar i0=0; i0<8; i0++) begin
// Field: dv_reg.StickyLockableScratchReg[].data
always_comb begin
automatic logic [31:0] next_c = field_storage.StickyLockableScratchReg[i0].data.value;
automatic logic load_next_c = '0;
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.StickyLockableScratchReg[i0].data.value;
load_next_c = '0;
if(decoded_reg_strb.StickyLockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchReg[i0].data.swwel)) begin // SW write
next_c = (field_storage.StickyLockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
Expand Down Expand Up @@ -435,7 +453,7 @@ module dv_reg (
logic readback_err;
logic readback_done;
logic [31:0] readback_data;

// Assign readback values to a flattened array
logic [304-1:0][31:0] readback_array;
for(genvar i0=0; i0<10; i0++) begin
Expand Down Expand Up @@ -490,4 +508,4 @@ module dv_reg (

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b)

endmodule
endmodule
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