Integrate abr into 2.0

chipsalliance · Sep 5, 2024 · 4b4ed45 · 4b4ed45
1 parent 5ca1be7
commit 4b4ed45
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Showing 170 changed files with 21,874 additions and 1,920 deletions.
diff --git a/src/aes/config/aes.vf b/src/aes/config/aes.vf
@@ -88,4 +88,4 @@ ${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
diff --git a/src/caliptra_prim/config/caliptra_prim.vf b/src/caliptra_prim/config/caliptra_prim.vf
@@ -59,4 +59,4 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
diff --git a/src/caliptra_prim/config/caliptra_prim_pkg.vf b/src/caliptra_prim/config/caliptra_prim_pkg.vf
@@ -6,3 +6,4 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
diff --git a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf
@@ -1,4 +1,4 @@
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
diff --git a/src/csrng/config/csrng_tb.vf b/src/csrng/config/csrng_tb.vf
@@ -103,4 +103,4 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
-${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
+${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
diff --git a/src/datavault/rtl/dv_reg.sv b/src/datavault/rtl/dv_reg.sv
@@ -235,10 +235,8 @@ module dv_reg (
  for(genvar i0=0; i0<10; i0++) begin
  // Field: dv_reg.StickyDataVaultCtrl[].lock_entry
  always_comb begin
- automatic logic [0:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value;
- load_next_c = '0;
+ automatic logic [0:0] next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.StickyDataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyDataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
  next_c = (field_storage.StickyDataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
  load_next_c = '1;
@@ -259,10 +257,8 @@ module dv_reg (
  for(genvar i1=0; i1<12; i1++) begin
  // Field: dv_reg.STICKY_DATA_VAULT_ENTRY[][].data
  always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value;
- load_next_c = '0;
+ automatic logic [31:0] next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.STICKY_DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
  next_c = (field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
  load_next_c = '1;
@@ -282,10 +278,8 @@ module dv_reg (
  for(genvar i0=0; i0<10; i0++) begin
  // Field: dv_reg.DataVaultCtrl[].lock_entry
  always_comb begin
- automatic logic [0:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.DataVaultCtrl[i0].lock_entry.value;
- load_next_c = '0;
+ automatic logic [0:0] next_c = field_storage.DataVaultCtrl[i0].lock_entry.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.DataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.DataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
  next_c = (field_storage.DataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
  load_next_c = '1;
@@ -306,10 +300,8 @@ module dv_reg (
  for(genvar i1=0; i1<12; i1++) begin
  // Field: dv_reg.DATA_VAULT_ENTRY[][].data
  always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value;
- load_next_c = '0;
+ automatic logic [31:0] next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
  next_c = (field_storage.DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
  load_next_c = '1;
@@ -329,10 +321,8 @@ module dv_reg (
  for(genvar i0=0; i0<10; i0++) begin
  // Field: dv_reg.LockableScratchRegCtrl[].lock_entry
  always_comb begin
- automatic logic [0:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
- load_next_c = '0;
+ automatic logic [0:0] next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.LockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
  next_c = (field_storage.LockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
  load_next_c = '1;
@@ -352,10 +342,8 @@ module dv_reg (
  for(genvar i0=0; i0<10; i0++) begin
  // Field: dv_reg.LockableScratchReg[].data
  always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.LockableScratchReg[i0].data.value;
- load_next_c = '0;
+ automatic logic [31:0] next_c = field_storage.LockableScratchReg[i0].data.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.LockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchReg[i0].data.swwel)) begin // SW write
  next_c = (field_storage.LockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
  load_next_c = '1;
@@ -374,10 +362,8 @@ module dv_reg (
  for(genvar i0=0; i0<8; i0++) begin
  // Field: dv_reg.NonStickyGenericScratchReg[].data
  always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.NonStickyGenericScratchReg[i0].data.value;
- load_next_c = '0;
+ automatic logic [31:0] next_c = field_storage.NonStickyGenericScratchReg[i0].data.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.NonStickyGenericScratchReg[i0] && decoded_req_is_wr) begin // SW write
  next_c = (field_storage.NonStickyGenericScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
  load_next_c = '1;
@@ -396,10 +382,8 @@ module dv_reg (
  for(genvar i0=0; i0<8; i0++) begin
  // Field: dv_reg.StickyLockableScratchRegCtrl[].lock_entry
  always_comb begin
- automatic logic [0:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value;
- load_next_c = '0;
+ automatic logic [0:0] next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.StickyLockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
  next_c = (field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
  load_next_c = '1;
@@ -419,10 +403,8 @@ module dv_reg (
  for(genvar i0=0; i0<8; i0++) begin
  // Field: dv_reg.StickyLockableScratchReg[].data
  always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.StickyLockableScratchReg[i0].data.value;
- load_next_c = '0;
+ automatic logic [31:0] next_c = field_storage.StickyLockableScratchReg[i0].data.value;
+ automatic logic load_next_c = '0;
  if(decoded_reg_strb.StickyLockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchReg[i0].data.swwel)) begin // SW write
  next_c = (field_storage.StickyLockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
  load_next_c = '1;
@@ -453,7 +435,7 @@ module dv_reg (
  logic readback_err;
  logic readback_done;
  logic [31:0] readback_data;
-
+ 
  // Assign readback values to a flattened array
  logic [304-1:0][31:0] readback_array;
  for(genvar i0=0; i0<10; i0++) begin
@@ -508,4 +490,4 @@ module dv_reg (
 
 `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b)
 
-endmodule
+endmodule