[RTL] Convert APB interfaces to AXI and add DMA (#590)

* Initial pass at AXI sub -- read channel only

* Compile for AXI sub

* AXI sub -- write channel + exclusive access fixups

* Exclusive access support OFF by default

* Only latch err from component when the access is allowed (i.e. not an incomplete EX access)

* Add AXI sub wrapper and simplex arbiter

* Syntax fix

* Add ID signal to component interface

* Add component inf 'write' signal

* New handshake assertions; i/f X checks conditional upon valid signals

* Swap APB for AXI, replace all 'user' references with 'AXI ID'

* axi_sub_wr: Fix rp valid/ready access

Ready & valid are 1-bit wide, do not access using bit select / range.

Signed-off-by: Wiktoria Kuna <[email protected]>

* axi_sub_arb: Fix arbiter read grant condition

When 'r_pri' is not set, read operation should be granted only if
a read 'r_dv' is pending and there's no required write action 'w_dv'.

Signed-off-by: Wiktoria Kuna <[email protected]>

* Remove LENB override; fix resp-pipe part-select in axi_sub_wr

* AXI sub tb integration -- compiles and passes smoke_test_hw_config

* Fixups to get sims working VCS + Verilator

* Initial AXI DMA reg file

* Format

* First pass - AXI DMA

* Caliptra AXI SRAM

* Defaults: AW=32, DW=64

* Mv skidbuffer to libs; add r/w error sigs in axi_sub to work with C_LAT>0; compile fixes for sram

* Syntax fix

* Add all module inst/connections; syntax fixes for compilation

* Include DMA reg set in docs

* Inst. DMA; connect SRAM through MBOX dir mode mux; add DMA regs in arb; upd COV IF

* Updates for AXI DMA connections

* AW should be derived from SRAM depth

* Add new reg fields; syntax cleanup to simulate; now passes smoke test

* Fix reset if-else syntax on ctx FF blocks

* Default assignment fix

* TB updates to support all prev. functionality; smoke_test_dma passes; add AXI assertions

* Update all caliptra_isr with new DMA interrupts; fw updates so all smoke tests pass

* Update HDL file lists

* Different init syntax for Verilator to compile vs VCS

* Update smoke_test_kv_hmac_multiblock_flow w/ DMA intr to pass compilation

* Add mailbox payload operations

* Default return of 0 for dma operations

* Reorder fail var assignment

* Fixes for DMA write and hold signaling to mailbox sram

* Fixes for credits and bytes requested calculations

* Move SoC BFM functionality to a sub-module in TB for reuse

* Add 1MiB xfer cap to cmd decode logic

* Rename s_axi_if to m_axi_bfm_if for clarity (in TB)

* Move caliptra_top_tb support files to separate compile pkg to avoid duplicate pre_exec calls (for importers)

* Enable BFM bringup to be skipped for SS testing

* Default AXI ID width is 8

* Support for path overrides by higher-level (SS) entity

* Add an enum for bootfsm states

* License header fixups

* Derive soc_ifc AXI ID widths from the global Caliptra macro

* Gen2 status disclaimer

* README timestamp

* No bold

* Use bash instead of sh in Makefile

* Regenerate file lists

* Add DMA interrupts

* Add DMA interrupts

* Synth pragmas to ignore sim-only tasks

* caliptra_prim is an axi_dma dependency

* Include assertion header where asserts are used

* Reorder a print message that is used as a trigger in OpenOCD tests

* File list updates after modifying dependencies

* Recommendations for release consumption

* Heading format

* Rewording for clarity

* Use 'assets' to match GH naming

* Convert skidbuffer reset to async, active-low

* Default AXI ID width of 8 matches Caliptra default - for clean lint

* Lint cleanup

* Lint fixes

* Lint fixes + fix for logic issue with large xfer calculations

* Width mismatch lint fixes

* Override DMA AXI manager Addr width for lint check

* Width mismatch lint fixes

* Use 'synopsys' pragma to disable sim code for synth/lint

* Syntax fix on loop indices; resolve a race condition at init time

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-gen2-axi-modules' with updated timestamp and hash after successful run

* Workaround for verilator compatibility

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-gen2-axi-modules' with updated timestamp and hash after successful run

* Re-enable check for sha/dma access on req_hold condition

* Fix the req_hold calculation for DMA transfers

* Apply active-low reset changes to the Formal properties in skidbuffer

* Remove OPT_INITIAL param and initialize regs with async reset

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-gen2-axi-modules' with updated timestamp and hash after successful run

---------

Signed-off-by: Wiktoria Kuna <[email protected]>
Co-authored-by: Wiktoria Kuna <[email protected]>

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-e3bfed2d8c8064b0c6f21410b619238538c01ad39f9763b67af8a958799d38c578cf4a9ac278bad8e2c0f4d471998b1a
+d5e1ab0f36f14576ade1380aa9c6985bbe6762062f358409e3be50ae7529bde17f5a9610cd26f37bef77679b69befb0c

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1726604628
+1727315247

README.md

@@ -14,8 +14,16 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2024/07/02*_
+_*Last Update: 2024/09/20*_
 
+:warning:**$${\textsf{\color{red}DISCLAIMER:\ This\ repository\ is\ under\ active\ development\ towards\ a\ Gen2\ release\ on\ branch\ main.}}$$**<br>
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;**$${\textsf{\color{red}Functionality\ or\ quality\ is\ not\ guaranteed.}}$$**<br>
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;**$${\textsf{\color{red}Do\ not\ integrate\ this\ into\ a\ production\ design!}}$$**<br>
+
+## **Release Consumption and Integration** ##
+Prior official releases are available at: https:/chipsalliance/caliptra-rtl/releases<br>
+Releases are published as a tag, and also contain downloadable assets (which should not be used).
+Instead of downloading the assets attached to the published release, integrators should consume Caliptra releases by pulling code from the repository at the associated tag, due to https:/chipsalliance/caliptra-rtl/issues/471.
 
 ## **Tools Used** ##
 

src/axi/config/axi_dma.vf

@@ -1,6 +1,9 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/axi/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
 ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
@@ -14,9 +17,53 @@ ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_req_if.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/axi/rtl/axi_dma_reg.sv

src/axi/config/compile.yml

@@ -45,6 +45,7 @@ provides: [axi_dma]
 schema_version: 2.4.0
 requires:
  - libs
+ - caliptra_prim
  - axi_pkg
 targets:
  rtl:

src/axi/rtl/axi_dma_ctrl.sv

@@ -74,6 +74,7 @@ import soc_ifc_pkg::*;
  // Imports //
  // --------------------------------------- //
  import axi_dma_reg_pkg::*;
+ `include "caliptra_prim_assert.sv"
 
 
  // --------------------------------------- //
@@ -151,12 +152,14 @@ import soc_ifc_pkg::*;
  logic [DW-1:0] r_data_mask;
 
  logic [AW-1:0] src_addr, dst_addr;
- logic [$clog2(FIFO_BC/BC+1)-1:0] rd_credits;
- logic [$clog2(FIFO_BC/BC+1)-1:0] wr_credits;
+ logic [FIFO_BW-1:0] rd_credits;
+ logic [FIFO_BW-1:0] wr_credits;
  logic [AXI_LEN_BC_WIDTH-1:0] block_size_mask;
  // 1's based counters
  logic [31:0] rd_bytes_requested;
+ logic rd_bytes_rem_thresh; // Number of read bytes remaining to be requested is lower than the threshold of MAX_BLOCK_SIZE
  logic [31:0] wr_bytes_requested;
+ logic wr_bytes_rem_thresh; // Number of write bytes remaining to be requested is lower than the threshold of MAX_BLOCK_SIZE
  logic [AXI_LEN_BC_WIDTH-1:0] rd_align_req_byte_count; // byte-count in a request until nearest AXI boundary
  logic [AXI_LEN_BC_WIDTH-1:0] rd_final_req_byte_count; // byte-count in the final request, which may be smaller than a typical request
  logic [AXI_LEN_BC_WIDTH-1:0] rd_req_byte_count; // byte-count calculated for the current read request
@@ -263,7 +266,7 @@ import soc_ifc_pkg::*;
  // Command Decode //
  // --------------------------------------- //
  generate
- if (AW < 32) begin
+ if (AW <= 32) begin
  always_comb begin
  src_addr = hwif_out.src_addr_l.addr_l.value[AW-1:0];
  dst_addr = hwif_out.dst_addr_l.addr_l.value[AW-1:0];
@@ -455,25 +458,27 @@ import soc_ifc_pkg::*;
 
  always_comb block_size_mask = hwif_out.block_size.size.value - 1;
  always_comb begin
- rd_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
- hwif_out.block_size.size.value - (r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
- rd_final_req_byte_count = hwif_out.byte_count.count.value - rd_bytes_requested;
+ rd_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
+ AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask));
+ rd_final_req_byte_count = rd_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - rd_bytes_requested) :
+ {AXI_LEN_BC_WIDTH{1'b1}};
  rd_req_byte_count = rd_final_req_byte_count < rd_align_req_byte_count ? rd_final_req_byte_count :
  rd_align_req_byte_count;
- wr_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
- hwif_out.block_size.size.value - (w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
- wr_final_req_byte_count = hwif_out.byte_count.count.value - wr_bytes_requested;
+ wr_align_req_byte_count = (~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value)) ? AXI_LEN_BC_WIDTH'(MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
+ AXI_LEN_BC_WIDTH'(hwif_out.block_size.size.value - (AXI_LEN_BC_WIDTH'(w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask));
+ wr_final_req_byte_count = wr_bytes_rem_thresh ? AXI_LEN_BC_WIDTH'(hwif_out.byte_count.count.value - wr_bytes_requested) :
+ {AXI_LEN_BC_WIDTH{1'b1}};
  wr_req_byte_count = wr_final_req_byte_count < wr_align_req_byte_count ? wr_final_req_byte_count :
  wr_align_req_byte_count;
  end
 
  always_comb begin
- r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count) && (rd_credits >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall;
+ r_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !rd_req_hshake_bypass && (rd_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(rd_credits) >= rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]) && !rd_req_stall;
  r_req_if.addr = src_addr + rd_bytes_requested;
  r_req_if.byte_len = rd_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
  r_req_if.fixed = hwif_out.ctrl.rd_fixed.value;
  r_req_if.lock = 1'b0; // TODO
- w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count) && (wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
+ w_req_if.valid = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count.value) && ((AXI_LEN_BC_WIDTH-BW)'(wr_credits) >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
  w_req_if.addr = dst_addr + wr_bytes_requested;
  w_req_if.byte_len = wr_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
  w_req_if.fixed = hwif_out.ctrl.wr_fixed.value;
@@ -508,30 +513,38 @@ import soc_ifc_pkg::*;
 
  always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
- rd_bytes_requested <= '0;
+ rd_bytes_requested <= '0;
+ rd_bytes_rem_thresh <= 1'b0;
  end
  else if (rd_req_hshake) begin
- rd_bytes_requested <= rd_bytes_requested + rd_req_byte_count;
+ rd_bytes_requested <= rd_bytes_requested + rd_req_byte_count;
+ rd_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (rd_bytes_requested + rd_req_byte_count)) >> AXI_LEN_BC_WIDTH);
  end
  else if (mb_dv && !mb_data.write && !mb_hold) begin
- rd_bytes_requested <= rd_bytes_requested + BC;
+ rd_bytes_requested <= rd_bytes_requested + BC;
+ rd_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (rd_bytes_requested + BC)) >> AXI_LEN_BC_WIDTH);
  end
  else if (ctrl_fsm_ps == DMA_IDLE) begin
- rd_bytes_requested <= '0;
+ rd_bytes_requested <= '0;
+ rd_bytes_rem_thresh <= ~|hwif_out.byte_count.count.value[31:AXI_LEN_BC_WIDTH];
  end
  end
  always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
- wr_bytes_requested <= '0;
+ wr_bytes_requested <= '0;
+ wr_bytes_rem_thresh <= 1'b0;
  end
  else if (wr_req_hshake) begin
- wr_bytes_requested <= wr_bytes_requested + wr_req_byte_count;
+ wr_bytes_requested <= wr_bytes_requested + wr_req_byte_count;
+ wr_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (wr_bytes_requested + wr_req_byte_count)) >> AXI_LEN_BC_WIDTH);
  end
  else if (mb_dv && mb_data.write && !mb_hold) begin
- wr_bytes_requested <= wr_bytes_requested + BC;
+ wr_bytes_requested <= wr_bytes_requested + BC;
+ wr_bytes_rem_thresh <= ~|((hwif_out.byte_count.count.value - (wr_bytes_requested + BC)) >> AXI_LEN_BC_WIDTH);
  end
  else if (ctrl_fsm_ps == DMA_IDLE) begin
- wr_bytes_requested <= '0;
+ wr_bytes_requested <= '0;
+ wr_bytes_rem_thresh <= ~|hwif_out.byte_count.count.value[31:AXI_LEN_BC_WIDTH];
  end
  end
 
@@ -542,11 +555,13 @@ import soc_ifc_pkg::*;
  else if ((ctrl_fsm_ps == DMA_IDLE) || (rd_req_hshake_bypass)) begin
  rd_credits <= FIFO_BC/BC;
  end
+ // Request byte count is restricted to not exceed the credit capacity
+ // Assertions (below) enforce a legal byte_count for sims
  else if (rd_req_hshake && (fifo_r_valid && fifo_r_ready)) begin
- rd_credits <= rd_credits + 1 - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
+ rd_credits <= rd_credits + 1 - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
  end
  else if (rd_req_hshake) begin
- rd_credits <= rd_credits - rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
+ rd_credits <= rd_credits - FIFO_BW'(rd_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
  end
  else if (fifo_r_valid && fifo_r_ready) begin
  rd_credits <= rd_credits + 1;
@@ -560,11 +575,13 @@ import soc_ifc_pkg::*;
  else if ((ctrl_fsm_ps == DMA_IDLE) || (wr_req_hshake_bypass)) begin
  wr_credits <= 0;
  end
+ // Request byte count is restricted to not exceed the credit capacity
+ // Assertions (below) enforce a legal byte_count for sims
  else if (wr_req_hshake && (fifo_w_valid && fifo_w_ready)) begin
- wr_credits <= wr_credits + 1 - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
+ wr_credits <= wr_credits + 1 - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
  end
  else if (wr_req_hshake) begin
- wr_credits <= wr_credits - wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW];
+ wr_credits <= wr_credits - FIFO_BW'(wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
  end
  else if (fifo_w_valid && fifo_w_ready) begin
  wr_credits <= wr_credits + 1;
@@ -694,12 +711,16 @@ import soc_ifc_pkg::*;
  // Requests must not cross AXI boundary (4KiB)
  `CALIPTRA_ASSERT(AXI_DMA_VLD_RD_REQ_BND, rd_req_hshake |-> r_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((r_req_if.addr + r_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_BND, wr_req_hshake |-> w_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((w_req_if.addr + w_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n)
+ // Proper configuration
  `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_32, DW == 32)
  `CALIPTRA_ASSERT_INIT(AXI_DMA_DW_EQ_MB, DW == MBOX_DATA_W)
+ // FIFO must have space for all requested data
  `CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC/BC, clk, !rst_n)
+ `CALIPTRA_ASSERT(AXI_DMA_OFL_RD_CRED, rd_req_hshake |-> rd_req_byte_count <= FIFO_BC, clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_MIN_RD_CRED, !((rd_credits < BC) && rd_req_hshake), clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_RST_RD_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (rd_credits == FIFO_BC/BC), clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_LIM_WR_CRED, wr_credits <= FIFO_BC/BC, clk, !rst_n)
+ `CALIPTRA_ASSERT(AXI_DMA_UFL_WR_CRED, wr_req_hshake |-> wr_credits >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW], clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_MIN_WR_CRED, !((wr_credits < BC) && wr_req_hshake), clk, !rst_n)
  `CALIPTRA_ASSERT(AXI_DMA_RST_WR_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (wr_credits == 0), clk, !rst_n)
 

src/axi/rtl/axi_if.sv

@@ -16,7 +16,7 @@
 // Signals for a standard AXI4 compliant interface
 //
 
-interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 3, parameter integer UW = 32) (input logic clk, input logic rst_n);
+interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 8, parameter integer UW = 32) (input logic clk, input logic rst_n);
 
  import axi_pkg::*;
 
@@ -155,6 +155,8 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
  input bready
  );
 
+ // synopsys translate_off
+
  // Tasks
  `ifdef VERILATOR
  `define EQ__ =
@@ -361,4 +363,6 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
  `undef EQ__
  `undef TIME_ALGN
 
+ // synopsys translate_on
+
 endinterface

src/axi/rtl/axi_mgr_rd.sv

@@ -45,6 +45,7 @@ module axi_mgr_rd import axi_pkg::*; #(
  // --------------------------------------- //
  // Imports //
  // --------------------------------------- //
+ `include "caliptra_prim_assert.sv"
 
 
  // --------------------------------------- //
@@ -92,11 +93,10 @@ module axi_mgr_rd import axi_pkg::*; #(
  .OPT_OUTREG (0 ),
  //
  .OPT_PASSTHROUGH(0 ),
- .DW ($bits(req_ctx_t)),
- .OPT_INITIAL (1'b1)
+ .DW ($bits(req_ctx_t))
  ) i_ctx_skd (
  .i_clk (clk ),
- .i_reset(!rst_n ),
+ .i_reset(rst_n  ),
  .i_valid(req_if.valid ),
  .o_ready(req_if.ready ),
  .i_data (req_ctx ),
@@ -107,13 +107,13 @@ module axi_mgr_rd import axi_pkg::*; #(
 
  always_ff@(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
- axi_ctx_sent = 1'b0;
+ axi_ctx_sent <= 1'b0;
  end
  else if (axi_ctx_valid && axi_ctx_ready) begin
- axi_ctx_sent = 1'b0;
+ axi_ctx_sent <= 1'b0;
  end
  else if (m_axi_if.arvalid && m_axi_if.arready) begin
- axi_ctx_sent = 1'b1;
+ axi_ctx_sent <= 1'b1;
  end
  end