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Add adamsbridge as a submodule
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Kiran Upadhyayula committed Oct 9, 2024
1 parent 205ce1f commit bc69589
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Showing 7 changed files with 17 additions and 3 deletions.
1 change: 1 addition & 0 deletions .github/workflows/build-test-verilator.yml
Original file line number Diff line number Diff line change
Expand Up @@ -187,6 +187,7 @@ jobs:
- name: Run Caliptra Verilator Smoke Test
run: |
CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd tools/scripts
make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name }} | tee output.log
# Search the last 30 lines of the output for "TESTCASE PASSED"
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8 changes: 8 additions & 0 deletions .github/workflows/interactive-debugging.yml
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Expand Up @@ -225,6 +225,7 @@ jobs:
- name: Build Verilated simulation
run: |
export CALIPTRA_ROOT=$(pwd)
export ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
mkdir run
make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \
OBJCACHE="" CC=gcc CXX=g++ LINK=g++
Expand All @@ -233,20 +234,23 @@ jobs:
- name: Test core register access
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd run
${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
/bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./dump_and_compare.sh'
- name: Test memory access
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd run
${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
/bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./mem_access.sh'
- name: Test peripheral access
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd run
${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
/bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./peripheral_access.sh'
Expand Down Expand Up @@ -300,6 +304,7 @@ jobs:
- name: Build Verilated simulation
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
mkdir run
make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 FORCE_CPU_RESET=1 \
OBJCACHE="" CC=gcc CXX=g++ LINK=g++
Expand All @@ -308,6 +313,7 @@ jobs:
- name: Test peripheral access with core in reset
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd run
${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \
-f board/caliptra-verilator-rst.cfg \
Expand All @@ -316,6 +322,7 @@ jobs:
- name: Build Verilated simulation
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
rm -rf run/*
make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \
OBJCACHE="" CC=gcc CXX=g++ LINK=g++
Expand All @@ -324,6 +331,7 @@ jobs:
- name: Test JTAG access with clock gating
run: |
export CALIPTRA_ROOT=$(pwd)
ADAMSBRIDGE_ROOT=$CALIPTRA_ROOT/submodules/adams-bridge
cd run
${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \
-f board/caliptra-verilator.cfg \
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3 changes: 3 additions & 0 deletions .gitmodules
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@@ -0,0 +1,3 @@
[submodule "submodules/adams-bridge"]
path = submodules/adams-bridge
url = https:/chipsalliance/adams-bridge
2 changes: 2 additions & 0 deletions README.md
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Expand Up @@ -141,6 +141,8 @@ caliptra-rtl
| |-- soc_ifc
| |-- spi_host
| `-- uart
|-- submodules
|-- adams-bridge
`-- tools
|-- README
|-- scripts
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3 changes: 1 addition & 2 deletions src/integration/rtl/caliptra_top.sv
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Expand Up @@ -934,8 +934,7 @@ hmac_ctrl #(

mldsa_top #(
.AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE),
.AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_MLDSA)),
.CLIENT_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE/2) //TODO confirm
.AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_MLDSA))
) mldsa (
.clk (clk_cg),
.rst_b (cptra_noncore_rst_b),
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2 changes: 1 addition & 1 deletion src/integration/rtl/config_defines.svh
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Expand Up @@ -56,7 +56,7 @@
`define CALIPTRA_SLAVE_SEL_IMEM 14
`define CALIPTRA_SLAVE_SEL_CSRNG 15
`define CALIPTRA_SLAVE_SEL_ENTROPY_SRC 16
`define CALIPTRA_SLAVE_SEL_MLDSA 17
`define CALIPTRA_SLAVE_SEL_MLDSA 17

// Interrupt Assignments
// NOTE Vector 0 is reserved by VeeR
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1 change: 1 addition & 0 deletions submodules/adams-bridge
Submodule adams-bridge added at 810175

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