Change module params from 2-state to 4-state logic in csrng

src/csrng/rtl/csrng.sv

@@ -15,7 +15,7 @@ module csrng
 #(
  parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplCanright,
  parameter logic [csrng_reg_pkg::NumAlerts-1:0] AlertAsyncOn = {csrng_reg_pkg::NumAlerts{1'b1}},
- parameter int NHwApps = 2,
+ parameter logic [31:0] NHwApps = 2,
  parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
  parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0),
  parameter AHBDataWidth = 64,

src/csrng/rtl/csrng_block_encrypt.sv

@@ -7,10 +7,10 @@
 
 module csrng_block_encrypt import csrng_pkg::*; #(
  parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
- parameter int Cmd = 3,
- parameter int StateId = 4,
- parameter int BlkLen = 128,
- parameter int KeyLen = 256
+ parameter logic [31:0] Cmd = 3,
+ parameter logic [31:0] StateId = 4,
+ parameter logic [31:0] BlkLen = 128,
+ parameter logic [31:0] KeyLen = 256
 ) (
  input logic clk_i,
  input logic rst_ni,

src/csrng/rtl/csrng_cmd_stage.sv

@@ -6,9 +6,9 @@
 //
 
 module csrng_cmd_stage import csrng_pkg::*; #(
- parameter int CmdFifoWidth = 32,
- parameter int CmdFifoDepth = 16,
- parameter int StateId = 4
+ parameter logic [31:0] CmdFifoWidth = 32,
+ parameter logic [31:0] CmdFifoDepth = 16,
+ parameter logic [31:0] StateId = 4
 ) (
  input logic clk_i,
  input logic rst_ni,

src/csrng/rtl/csrng_core.sv

@@ -13,7 +13,7 @@ module csrng_core
  import lc_ctrl_pkg::*;
 #(
  parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
- parameter int NHwApps = 2,
+ parameter logic [31:0] NHwApps = 2,
  parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
  parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0)
 ) (

src/csrng/rtl/csrng_ctr_drbg_cmd.sv

@@ -7,12 +7,12 @@
 // Accepts all csrng commands
 
 module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
- parameter int Cmd = 3,
- parameter int StateId = 4,
- parameter int BlkLen = 128,
- parameter int KeyLen = 256,
- parameter int SeedLen = 384,
- parameter int CtrLen = 32
+ parameter logic [31:0] Cmd = 3,
+ parameter logic [31:0] StateId = 4,
+ parameter logic [31:0] BlkLen = 128,
+ parameter logic [31:0] KeyLen = 256,
+ parameter logic [31:0] SeedLen = 384,
+ parameter logic [31:0] CtrLen = 32
 ) (
  input logic clk_i,
  input logic rst_ni,

src/csrng/rtl/csrng_ctr_drbg_gen.sv

@@ -9,13 +9,13 @@
 // ctr_drbg cmd module.
 
 module csrng_ctr_drbg_gen import csrng_pkg::*; #(
- parameter int NApps = 4,
- parameter int Cmd = 3,
- parameter int StateId = 4,
- parameter int BlkLen = 128,
- parameter int KeyLen = 256,
- parameter int SeedLen = 384,
- parameter int CtrLen = 32
+ parameter logic [31:0] NApps = 4,
+ parameter logic [31:0] Cmd = 3,
+ parameter logic [31:0] StateId = 4,
+ parameter logic [31:0] BlkLen = 128,
+ parameter logic [31:0] KeyLen = 256,
+ parameter logic [31:0] SeedLen = 384,
+ parameter logic [31:0] CtrLen = 32
 ) (
  input logic clk_i,
  input logic rst_ni,

src/csrng/rtl/csrng_ctr_drbg_upd.sv

@@ -7,12 +7,12 @@
 // implementation using security_strength = 256
 
 module csrng_ctr_drbg_upd #(
- parameter int Cmd = 3,
- parameter int StateId = 4,
- parameter int BlkLen = 128,
- parameter int KeyLen = 256,
- parameter int SeedLen = 384,
- parameter int CtrLen = 32
+ parameter logic [31:0] Cmd = 3,
+ parameter logic [31:0] StateId = 4,
+ parameter logic [31:0] BlkLen = 128,
+ parameter logic [31:0] KeyLen = 256,
+ parameter logic [31:0] SeedLen = 384,
+ parameter logic [31:0] CtrLen = 32
 ) (
  input logic clk_i,
  input logic rst_ni,
@@ -312,7 +312,7 @@ module csrng_ctr_drbg_upd #(
  interate_ctr_inc ? (interate_ctr_q + 1) :
  interate_ctr_q;
 
- assign interate_ctr_done = (int'(interate_ctr_q) >= SeedLen/BlkLen);
+ assign interate_ctr_done = (32'(interate_ctr_q) >= SeedLen/BlkLen);
 
  //--------------------------------------------
  // state machine to send values to block_encrypt
@@ -507,7 +507,7 @@ module csrng_ctr_drbg_upd #(
  concat_ctr_inc ? (concat_ctr_q + 1) :
  concat_ctr_q;
 
- assign concat_ctr_done = (int'(concat_ctr_q) >= (SeedLen/BlkLen));
+ assign concat_ctr_done = (32'(concat_ctr_q) >= (SeedLen/BlkLen));
 
  assign concat_inst_id_d =
  (!ctr_drbg_upd_enable_i) ? '0 :

src/csrng/rtl/csrng_pkg.sv

@@ -9,11 +9,11 @@ package csrng_pkg;
  // Application Interfaces
  //-------------------------
 
- parameter int unsigned GENBITS_BUS_WIDTH = 128;
- parameter int unsigned CSRNG_CMD_WIDTH = 32;
- parameter int unsigned FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
+ parameter logic [31:0] GENBITS_BUS_WIDTH = 128;
+ parameter logic [31:0] CSRNG_CMD_WIDTH = 32;
+ parameter logic [31:0] FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH +
  GENBITS_BUS_WIDTH;
- parameter int unsigned MainSmStateWidth = 8;
+ parameter logic [31:0] MainSmStateWidth = 8;
 
  // instantiation interface
  typedef struct packed {
@@ -85,7 +85,7 @@ package csrng_pkg;
  MainSmError = 8'b01111000 // error state, results in fatal alert
  } main_sm_state_e;
 
- parameter int CsKeymgrDivWidth = 384;
+ parameter logic [31:0] CsKeymgrDivWidth = 384;
  typedef logic [CsKeymgrDivWidth-1:0] cs_keymgr_div_t;
 
 endpackage : csrng_pkg

src/csrng/rtl/csrng_reg_pkg.sv

@@ -7,10 +7,10 @@
 package csrng_reg_pkg;
 
  // Param list
- parameter int NumAlerts = 2;
+ parameter logic [31:0] NumAlerts = 2;
 
  // Address widths within the block
- parameter int BlockAw = 7;
+ parameter logic [31:0] BlockAw = 7;
 
  ////////////////////////////
  // Typedefs for registers //

src/csrng/rtl/csrng_state_db.sv

@@ -10,12 +10,12 @@
 `include "caliptra_prim_assert.sv"
 
 module csrng_state_db import csrng_pkg::*; #(
- parameter int NApps = 4,
- parameter int StateId = 4,
- parameter int BlkLen = 128,
- parameter int KeyLen = 256,
- parameter int CtrLen = 32,
- parameter int Cmd = 3
+ parameter logic [31:0] NApps = 4,
+ parameter logic [31:0] StateId = 4,
+ parameter logic [31:0] BlkLen = 128,
+ parameter logic [31:0] KeyLen = 256,
+ parameter logic [31:0] CtrLen = 32,
+ parameter logic [31:0] Cmd = 3
 ) (
  input logic clk_i,
  input logic rst_ni,