[ECC] add_sub_mod_alter ready not aligned with result

[ludwigatlubis]

Hello,

We found an issue with the ready signal which does not align with the computed result. The expected behaviour of the ready signal is to be set when we have the correct result. In the current implementation the ready arrives 1-2 cycles, if and only if the enable signal is kept low.

@mojtaba-bisheh confirmed this issue, however, the design works fine with the current implementation, because it does not affect the computation itself. It will be updated in future releases.

We adde two sets of constraints for this module. One that includes the intended input behaviour and one that fixes the current issues appended with _bugfix. Please remove that constraint after the RTL design updates are done to check for correctness.

Best
Tobias

[mojtaba-bisheh]

We did not use the ready signal in the design because we hard coded the arithmetic scheduling. But we have fixed this issue in our internal repo and we will update it here soon. (https:/chipsalliance/caliptra-rtl/pull/193/commits has this fix)
The next enhancement for the adder is to remove the constraint that requires constant inputs during the computation. This will make the architecture more reusable for other designs.