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[Integration spec] Document full cold boot flow from integrator perspective #334

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jhand2 opened this issue Dec 6, 2023 · 5 comments · Fixed by #349
Closed

[Integration spec] Document full cold boot flow from integrator perspective #334

jhand2 opened this issue Dec 6, 2023 · 5 comments · Fixed by #349
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@jhand2
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jhand2 commented Dec 6, 2023

I wasn't able to find documentation of the things an integrator is supposed to do to boot Caliptra. Steps like:

  1. Assert CPTRA_POWER_GOOD
  2. Populate fuse registers
  3. Write fuse_write_done register
  4. Write BOOTFSM_GO register

Is this something that would make sense to document in the hardware integration spec.

@Nitsirks
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Nitsirks commented Dec 6, 2023

I think this figure in that doc is meant to detail that.

Figure 3: Reset rules and timing diagram

@bharatpillilli maybe we can be more explicit in the spec so the information is easier to find?

@jhand2
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jhand2 commented Dec 6, 2023

Got it, that diagram is helpful. Ya I think it would be good to explicitly list what is expected from the SoC. In particular, I don't think it says the SoC needs to assert BOOTFSM_GO.

@bharatpillilli
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I think this figure in that doc is meant to detail that.

Figure 3: Reset rules and timing diagram

@bharatpillilli maybe we can be more explicit in the spec so the information is easier to find?

Ack Mike!

@bharatpillilli
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bharatpillilli commented Dec 8, 2023

BootFSM Go is only required when HW Break point is set -otherwise it should not be gating

@jhand2
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jhand2 commented Dec 8, 2023

BootFSM Go is only required when HW Break point is set -otherwise it should not be gating

Ah, I didn't know that. Thanks for the clarification.

Nitsirks added a commit that referenced this issue Dec 11, 2023
Removed references to TSMC 5nm process. Closes #348 
Clarified reset rules section to reference cold boot flow to be easier to find for integrators. Closes #334 
Removed TODO from lint rules section. Closes #338
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3 participants