Merge dev-msft --> dev-integrate #192
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Add a new mailbox SRAM interface/agent to UVM environment with an SRAM model implementation. Run a responder sequence to service all SRAM transfers, and enable ECC error injection/detection at the sram interface. Enable random injection of errors (single-bit only, currently) into both UVMF_SOC_IFC and UVMF_CALIPTRA_TOP random regression tests. Related work items: #502507, #502532
added SVA and coverage for modular operations Related work items: #520637
- Made the fuse valid pauser registers sticky, allowing them to be used during fuse download instead of held under reset. - Updated the fuse pauser test in soc ifc tb - Appropriately staged the reset window logic so it doesn't create it's own RDC issue. - Forced more logic IDLE in the 2:1 ahb mux during fw update reset. - Provided RDC only gated clock to veer core to resolve the RDC crosses into debug logic. Related work items: #518239, #518350
Add testcases that randomly inject invalid/illegal mailbox register accesses during a regular mailbox flow. Testcases are added to inject invalid register accesses for both SOC->UC and UC->SOC mailbox flows in this PR. (only APB invalid reg accesses are performed, to validate the protocol error path). Invalid register accesses are defined (as in the integration spec) as writes to an register (or reads from dataout) at an unexpected stage of the flow (i.e., write to clear execute when the responder has not yet returned control to the sender). The soc_ifc UVM bench also includes new code to initialize interrupts and service error events when they occur to restore the mailbox state. Also added a fix for a minor issue in the mailbox - certain fsm 'arc' signals toggled in the incorrect state (not a functional issue, but a power optimization). Related work items: #442339, #442340, #442948, #442949, #495747, #521329
…ox status Added current mailbox read pointer to the mailbox status register. Adding a new sequence to have runtime FW use the direct read path in the mailbox. Fixing a bug in the 2:1 ahb mux that could cause a hang. Related work items: #443133, #460321, #522026
- fixed mont mult bug in last reduction found by FPV - fixed last mult reduction coverpoint - added montgomery_tb for corner cases and updated vf files Related work items: #522088
UVM updates and sequence to: 1. Enable WDT in cascade mode with default timeout values during ROM execution 2. Test cascade mode (with t1 timeout) and independent mode randomly during runtime TODO: 1. Test t2 expiry in cascade mode which triggers NMI (test hangs due to RDC issues when a reset is issued to service the NMI) Related work items: #468167, #468170
Fixing the debug unlock logic to check the appropriate signals now. Various fixes to soc ifc tb to fix new failures due to new fuse register and new field in cptra flow status Related work items: #527001
Update UVM predictor to account for timing changes in BOOT FSM and internal reset signals due to RDC logic changes Also: * UVM bug fix for incorrect prediction of soc_req_lock interrupt * UVM bug fix for handling of WDT resets and service events * UVM reg-model update to define "NONCORE" reset type for registers instead of the previous "SOFT" reset type * UVM enhancement in the reg-model to enforce that custom reset definitions for each register block is up-to-date Related work items: #471227, #515204, #529427, #529732
added pcr invalid command fixed add_ready_o Related work items: #527023
…of cptra_rst_b instead of waiting for fuse wr done - bring APB interface onto the noncore reset domain - cause noncore reset to deassert earlier - fix for bug 530394 suppressing kv writes during clear, could still cause a race condition - fix for bug 530517 ensuring breakpoint is still reachable after moving latched values to noncore reset This PR also includes: - Fixes for detection/prediction of fw_update_rst_window on cptra_status_if - Enhancements to promote pipeline to run slightly more rigorous UVM test cases to hopefully catch deadlock earlier Related work items: #298952, #530394, #530517
Updated ROM with image that correctly handles the SHA Accel Lock init, resolves timeout in regressions. Added TRNG support to ROM UVM test, with regression flows for INTERNAL/EXTERNAL TRNG modes. Related work items: #529197
Fixes for errors from Nightly Random Regression, August 21 2023. * Updated interrupt handler routine at the end of Caliptra-initiated mbox flow test sequence to capture random events that might occur (protocol violations, ECC errors, soc_req_lock events that are randomly injected). * Updated protocol error prediction logic to avoid predicting duplicate interrupts for the same error. Related work items: #532442, #532445
Updates to KV UVM to accommodate changes around debug and clear functionality Test to issue resets with contents in ICCM/DCCM TODO: fw_update_rst_window support in KV UVM
…t enable ecc decode - fixing enable to ecc decode for SHA accelerator reads of the mailbox - adding 2ff synchronizer module to aid with RDC validation - implemented new entropy src health test registers for github issue 190 Related work items: #298952, #532683, #532813
Dev msft 20230813
calebofearth
approved these changes
Aug 24, 2023
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