Dev msft 03022023

.github/workflows/doc-gen.yml

@@ -0,0 +1,63 @@
+# docs: https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions
+
+name: Register Documentation
+
+on:
+ workflow_dispatch:
+ pull_request:
+ push:
+ branches: ["main"]
+
+jobs:
+ build:
+ name: Build
+
+ runs-on: ubuntu-22.04
+
+ steps:
+ - uses: actions/checkout@v3
+
+ - name: Install peakrd-uvm
+ run: |
+ python3 -m pip install \
+ peakrdl-uvm==2.2.0 \
+ peakrdl-regblock==0.10.0 \
+ peakrdl-html==2.9.0 \
+ peakrdl-ipxact==3.3.0
+
+ - name: Generate docs
+ run: |
+ echo Running script
+ tools/scripts/reg_doc_gen.sh
+
+ - name: Stage documents
+ run: |
+ mkdir -p /tmp/pages-docs/main
+ cp -R src/integration/docs/caliptra_reg_html /tmp/pages-docs/main/internal-regs
+ cp -R src/soc_ifc/docs/caliptra_top_reg_html /tmp/pages-docs/main/external-regs
+ find /tmp/pages-docs
+
+ - name: Generate GitHub Pages artifacts
+ uses: actions/upload-pages-artifact@v1
+ with:
+ path: /tmp/pages-docs
+
+ deploy:
+ name: Deploy
+ needs: build
+ if: github.event_name == 'push'
+
+ permissions:
+ pages: write
+ id-token: write
+
+ environment:
+ name: github-pages
+ url: ${{ steps.deployment.outputs.page_url }}
+
+ runs-on: ubuntu-22.04
+
+ steps:
+ - name: Deploy to GitHub Pages
+ id: deployment
+ uses: actions/deploy-pages@v1

.gitignore

@@ -0,0 +1,2 @@
+src/integration/docs/caliptra_reg_html/
+src/soc_ifc/docs/caliptra_top_reg_html/

LICENSE

@@ -1,3 +1,4 @@
+
  Apache License
  Version 2.0, January 2004
  http://www.apache.org/licenses/

README.md

@@ -1,5 +1,6 @@
 _*SPDX-License-Identifier: Apache-2.0<BR>
 <BR>
+<BR>
 Licensed under the Apache License, Version 2.0 (the "License");<BR>
 you may not use this file except in compliance with the License.<BR>
 You may obtain a copy of the License at<BR>
@@ -12,14 +13,11 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.<BR>
 See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
-# **Caliptra RTL Hands-On Guide** #
-_*Last Update: 2023/01/23*_
+# **Caliptra Hands-On Guide** #
+_*Last Update: 2023/03/02*_
 
 [[_TOC_]]
 
-## **Overview** ##
-RTL and Verification for Caliptra RoT IP.
-
 ## **Tools Used** ##
 
 OS:
@@ -67,18 +65,22 @@ Required for Firmware (i.e. Test suites) makefile:<BR>
 Caliptra
 |-- LICENSE
 |-- README.md
-|-- VERSION.txt
 |-- Release_notes.txt
-|-- Coming_soon.txt
+|-- docs
+| |-- Caliptra_Integration_Specification.pdf
+| |-- Caliptra_Hardware_Spec.pdf
+| |-- Caliptra_TestPlan_L1.pdf
 |-- src
 | |-- ahb_lite_bus
+| |-- datavault
 | |-- doe
 | |-- ecc
 | |-- hmac
 | |-- hmac_drbg
 | |-- integration
 | |-- keyvault
 | |-- libs
+| |-- pcrvault
 | |-- riscv_core
 | |-- sha256
 | |-- sha512
@@ -105,7 +107,7 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr
 `rdl_post_process.py`: Post-processing functionality to make RDL generated SystemVerilog files compatible with lint/Verilator requirements<BR>
 `run_verilator_l0_regression.py`: Wrapper to run the L0 smoke test regression suite using the Makefile flow in Verilator<BR>
 `integration_vector_gen.py`: Generates test vectors for crypto core tests<BR>
-`swerv_build_command.sh`: Shell script used to generate the SweRV-EL2 repository present in `src/riscv_core/swerv_el2`<BR>
+`veer_build_command.sh`: Shell script used to generate the VeeR-EL2 repository present in `src/riscv_core/veer_el2`<BR>
 
 ## **Simulation Flow** ##
 VCS Steps:

Release_notes.txt

@@ -1,7 +1,52 @@
+_*Last Update: 2023/03/02*_
+
 # Release_notes.txt
-# Stores revision information for rtl-caliptra
+# Stores revision information for caliptra-rtl
+
+Pre0p8 release notes:
+- DISCLAIMER: This is NOT A BUG-FREE MODEL. This is a pre-0p8 development model that will be sync’d every week. 
+ - This model is released mainly for interface, floorplan planning purposes for consumers.
+ - 0p8 release date = 03-31-2023
+- Caliptra Hardware Specification: see docs/ folder
+- Caliptra Integration Specification: see docs/ folder
+- Caliptra testplan: see docs/ folder
+- CHIPALLIANCE RISC-V Core - https:/chipsalliance/Cores-VeeR-EL2/
+ - ICCM, DCCM enabled w/ 128KB each; Instruction Cache disabled; fast interrupt redirect enabled
+- Cryptos (please see the spec for NIST compliance algorithms followed)
+ - HMAC384 – Caliptra consortium provided (built based on SHA384 block below)
+ - ECC384 – Based on secp384, Caliptra consortium provided
+ - HMAC-DRBG – Caliptra consortium provided (but built using HMAC384 above)
+ - Key Vault & PCR Vault – Caliptra consortium provided
+ - SHA384/SHA512 – https:/secworks/sha512
+ - Deobfuscation block – Built on https:/secworks/aes but NOT ROM/FW accessible
+ - SHA256 – https:/secworks/sha256
+ - Side channel attack analysis and solutions where applicable (Plz see Caliptra IP specification for details)
+- AHB-lite internal fabric
+ - Please see spec for decoding details of various blocks
+- Key Vault, PCR Vault w/ HW PCR extension & Data Vault
+- Interrupts from all peripherals (Cryptos, SOC mailbox, IOs, timers etc.)
+- ICCM write locking
+- TAP interface
+- Idle Clock Gating
+- Impactless update reset
+- Mailbox SRAM ECC
+- Security Assert Flushing in debug unlocked & scan modes
+- SOC interface (APB, mailbox, architectural registers, fuse registers, external TRNG REQ, SHA384 acceleration) – Caliptra Consortium provided
+- Lint clean to the rules published in the integration spec
+- HTML (generated from RDLs) for all registers (internal registers, external facing architectural registers, fuse registers)
+- RTL “Frozen” IP interface; Frozen SOC facing registers.
+ - All changes from hereon forth will require CHIPSALLIACE CALIPTRA WG approval
+- Validation Notes:
+ - DUT per crypto block and associated checkers
+ - Nightly regression on crypto blocks on-going
+ - Smoke tests for all of the above passing including bring up/boot of the caliptra IP (KV testing for ECC & SHA)
+ - UVMF for multiple DUT blocks and SOC interface
 
-Rev rtl-caliptra_rtl_0.5
+Rev rtl-caliptra_rtl_0.5.1
+- Add missing printf/ and includes/ directories to src/integration/test_suites which are required to run the tests
+- Updated Version.txt and tar.gz
+
+Rev rtl-caliptra_rtl_0.5rtl
 - CHIPALLIANCE RISC-V Core - https:/chipsalliance/Cores-VeeR-EL2
  - ICCM, DCCM enabled w/ 128KB each; Instruction Cache disabled; fast interrupt redirect enabled
 - Cryptos (please see the spec for NIST compliance algorithms followed)
@@ -28,7 +73,11 @@ Rev rtl-caliptra_rtl_0.5
  - UVMF for multiple DUT blocks and SOC interface
  - NOTE: 0p8 release will have stress validation on SOC interface with random resets, clock gating, impactless update crossed with mailbox protocol etc.
 
-Rev rtl-caliptra_rtl_0.5.1
-- Add missing printf/ and includes/ directories to src/integration/test_suites which are required to run the tests
-- Updated Version.txt and tar.gz
+UPCOMGING CHANGES:
+
+RTL 0p8 Pending (Target):
+- Timers, integrated-TRNG integration w/ Caliptra, Error domain logic
+- Lots of bug fixes :-)
+- DV complete of boot flow, reset flow, Fuses, SOC registers, Crypto blocks, Key vault, PCR Vault, Data Vault, TRNG REQ protocol, SHA384 acceleration
+
 

src/ahb_lite_bus/config/ahb_lite_bus.vf

@@ -0,0 +1,5 @@
++incdir+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv

src/ahb_lite_bus/config/ahb_node_wrap.vf

@@ -0,0 +1,4 @@
++incdir+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_bus.sv
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_node.sv
+${WORKSPACE}/Caliptra/src/ahb_lite_bus/rtl/ahb_node_wrap.sv

src/ahb_lite_bus/config/compile.yml

@@ -0,0 +1,17 @@
+---
+provides: [ahb_lite_bus]
+schema_version: 2.4.0
+targets:
+ rtl:
+ directories: [$COMPILE_ROOT/rtl]
+ files:
+ - $COMPILE_ROOT/rtl/ahb_lite_bus_inf.sv
+ - $COMPILE_ROOT/rtl/ahb_lite_address_decoder.sv
+ - $COMPILE_ROOT/rtl/ahb_lite_bus.sv
+ - $COMPILE_ROOT/rtl/ahb_lite_2to1_mux.sv
+ tops: [ahb_lite_bus]
+ rtl_lint:
+ directories: []
+ waiver_files: 
+ - $COMPILE_ROOT/config/design_lint/ahb_lite_bus/sglint_waivers
+