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Specify TRNG timing requirement #361

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Dec 20, 2023
Merged

Specify TRNG timing requirement #361

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Specify TRNG timing requirement
andreslagarcavilla Dec 19, 2023
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andreslagarcavilla Dec 19, 2023
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andreslagarcavilla Dec 20, 2023
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4 changes: 4 additions & 0 deletions docs/CaliptraIntegrationSpecification.md
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Expand Up @@ -476,6 +476,10 @@ Having an interface that is separate from the SoC mailbox ensures that this requ

TRNG DATA register is tied to TRNG VALID PAUSER. SoC can program the TRNG VALID PAUSER and lock the register using TRNG\_PAUSER\_LOCK[LOCK]. This ensures that TRNG DATA register is read-writeable by only the PAUSER programmed into the TRNG\_VALID\_PAUSER register. If the CPTRA\_TNRG\_PAUSER\_LOCK.LOCK is set to ‘0, then any agent can write to the TRNG DATA register. If the lock is set, only an agent with a specific TRNG\_VALID\_PAUSER can write.

The ROM and firmware currently time out on the TRNG interface after 250,000
attempts to read a DONE bit. This bit is set in the architectural registers, as
referenced in 3 in the preceding list.

# SRAM implementation

## Overview
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