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Preprocessor Documentation issue #2215

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a-kest opened this issue Jul 13, 2024 · 2 comments
Open

Preprocessor Documentation issue #2215

a-kest opened this issue Jul 13, 2024 · 2 comments
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rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).

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@a-kest
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a-kest commented Jul 13, 2024

Hello in issues there wasnt a selection for the preprocessor so I took the closest I found.

Describe the bug

In https:/chipsalliance/verible/tree/master/verilog/tools/preprocessor README it says to use the +include+ flag to include directories, however this does not work. Instead +incdir+ should be used I guess.
@a-kest a-kest added the rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017). label Jul 13, 2024
@hzeller
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hzeller commented Jul 15, 2024

Yes, looks like a typo. Can you send a pull request fixing it ? It is indeed +incdir+.

@a-kest a-kest mentioned this issue Jul 18, 2024
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@a-kest
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a-kest commented Jul 18, 2024

Done. Thank you.

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rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
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@hzeller @a-kest