Detect data type and rvalue width mismatches

[benjamin051000]

Summary

I'd like the ability to detect when an assignment has differing widths, and a warning that comes with it.

Test cases and examples
In the below example, address silently resolves to a value of 0 in QuestaSim.

localparam logic address = 32'hfffc; // BUG 'logic' does not match rvalue width of 32!

---

In the below example, sixteen is silently extended (I'm not sure if it's signed/arithmetic extension, either).

initial begin
    logic [31:0] thirtytwo = 32'habcdef;
    logic [15:0] sixteen = 16'hffff;

    // WARNING: (signed?) extension implicitly performed on `sixteen`
    if (thirtytwo == sixteen) begin
        // ...
    end
end

Proposal

Create a warning that checks for these width mismatches. Explicitly matching the widths via tools like WIDTH'(expression) can resolve the warning.

Additional Context
Even though this is a well-documented "feature" of (system)verilog, it can hide nasty bugs. In this case, explicit is better than implicit!