using tick define for delay doesn't work

[vanjoe]

Describe the bug

When I use a `define to specify a delay the parser says there is a syntax error.

To Reproduce
Run the following code through verible-verilog-syntax I

`ifndef ASSIGN_DELAY
 `define ASSIGN_DELAY #0
`endif
module test
#()
  (
   input a,clk,
   output b);
  reg bb;



  always_ff @(posedge clk) begin
    bb <= `ASSIGN_DELAY a;
  end
  assign b = bb;
endmodule

Actual behavior:

The command reports

test.v:14:25: syntax error at token "a"

Expected behavior

I expect no output indicating success.