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Is it possible to leave all lines whose beginning wasn't moved as they are? (i.e. to prevent any internal indentation within the line) #2237

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avidan-efody opened this issue Aug 18, 2024 · 0 comments
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formatter Verilog code formatter issues

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@avidan-efody
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i.e. for this code:

class bla_c;
    parameter xxx               = 5;
    parameter yyy               = 6;
endclass

variable would give the following (I have tried all preserve options):

class bla_c;
    parameter xxx = 5;
    parameter yyy = 6;
endclass

Is it possible to leave these lines as they were since the beginning wasn't moved? i.e. :

class bla_c;
    parameter xxx               = 5;
    parameter yyy               = 6;
endclass
@avidan-efody avidan-efody added the formatter Verilog code formatter issues label Aug 18, 2024
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Labels
formatter Verilog code formatter issues
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