Formatter splits label from assertion on new line unnecessarily

[hankhsu1996]

Test case

module add (
    input  logic        clk,
    input  logic        reset,
    input  logic [31:0] a,
    input  logic [31:0] b,
    output logic [31:0] sum,
    output logic        carry
);

  assign {carry, sum} = a + b;

  // If sum < a or sum < b, then carry = 1
  carry_check: assert property (
    @(posedge clk) disable iff (reset)
    (sum < a) |-> carry == 1);

endmodule

Actual output

carry_check :
assert property (@(posedge clk) disable iff (reset) (sum < a) |-> carry == 1);

Expected or suggested output

carry_check: assert property (
    @(posedge clk) disable iff (reset)
    (sum < a) |-> carry == 1);

I would prefer the label and the assertion to remain on the same line, and the assertion body to be formatted over multiple lines for readability. It seems there is currently no option in the formatter to control this behavior.