Update STM32 RCC U5 to support P and Q dividers #2396
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Dirbaio
reviewed
Jan 3, 2024
embassy-stm32/src/rcc/u5.rs
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| @@ -45,6 +45,18 @@ pub struct PllConfig { | |||
| /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544 | |||
| /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`. | |||
| pub n: Plln, | |||
| /// The divider for the P output. | |||
| /// | |||
| /// When used to drive the system clock, `source` divided by `m` times `n` divided by `r` | |||
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this comment is not relevant for p/q, only r can drive the system clock.
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Sounds good. I will update.
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Updated the comments.
Update comments on p and q divider values to correctly describe what the clock outputs are used for.
Dirbaio
approved these changes
Jan 3, 2024
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This MR adds support for setting the P and Q dividers in the STM32 U5 RCC. This is used when setting the SAI clock.