[chip-test] chip_sw_power_idle_load

[msfschaffner]

Test point name

chip_sw_power_idle_load

Host side component

SystemVerilog+Rust

OpenTitanTool infrastructure implemented

Unknown

Contact person

@tjaychen and @msfschaffner for HW, @timothytrippel @sriyerg for DV and concurrency framework

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• HJSON test plan updated with test name (so it shows up in the dashboard)
• Test added to dvsim nightly regression (and passing at time of checking)

[johngt]

@tjaychen / @msfschaffner - based on comment #14814 (comment) should this also be moved to post M2?
Otherwise we will need an update on the status of this from @yehuda-bejar

[tjaychen]

i think the one that was lowered is the max power concurrency test, but the not the idle load one.

[msfschaffner]

Yeah this idle test should be ready soon, see #15923.

[msfschaffner]

Closing this as it is passing in nightlies. Any further FPGA debugging will be tracked in a test triage issue.

[moidx]

Created #16506 to track FPGA issue.