[chip-test] chip_sw_power_max_load #14814

msfschaffner · 2022-09-07T19:59:37Z

Test point name

chip_sw_power_max_load

Host side component

SystemVerilog+Rust

OpenTitanTool infrastructure implemented

Unknown

Contact person

@tjaychen @msf for HW, @timothytrippel @sriyer for DV and concurrency framework

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
Device-side (C) component developed
Bazel build rules developed
Host-side component developed
HJSON test plan updated with test name (so it shows up in the dashboard)
Test added to dvsim nightly regression (and passing at time of checking)

timothytrippel · 2022-10-04T22:47:21Z

See #14095 for more details.

This adds the boilerplate code for the power virus test to partially address lowRISC#14814. Since this test will be rather large/complex, it will be committed in pieces over time. This initial commit contains a basic test checklist (that will be added-to/improved over time) and basic configurations for the pinmux, gpio, and adc_ctrl peripherals. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel · 2022-10-28T21:47:40Z

Test Checklist (WIP):

(Task 0) Main:

(Task 1) Block Loading Operations:

write data to AES FIFO ([test] add several tasks to power virus tests to actuate IPs #17030)
write data to HMAC FIFO ([test] add several tasks to power virus tests to actuate IPs #17030)
write data to KMAC FIFO ([test] add several tasks to power virus tests to actuate IPs #17030)
write program/data to OTBN IMEM/DMEM ([test] exercise OTBN in power virus test #17284)
write data to all three UART FIFOs ([test] add several tasks to power virus tests to actuate IPs #17030)
write data to all three I2C FIFOs ([test] connect UARTs/I2Cs to pins and TX data on I2Cs in power virus test #17126)
write data to SPI host 1 (non-passthrough block) FIFO ([test] drive SPI host 1 in power virus test #17248)

(Task 2) Activate All Blocks and Check results

OTP Test Parameters:

turn on flash scrambling and ECC ([util,test] fix bug in flash scrambling script and add flash scrambling smoketest #17575)

Host Side (DV sequence) Test Component:

add DV sequence boilerplate ([test] add initial SV host component for power virus test #17089)
ack I2C transactions and check for correctness ([test] Add I2C acknowledgement to power virus test #17556)
configure/drive spi_device (in passthrough mode) during time of max power epoch ([test] Add spi_passthrough support to the power virus test #17747)
check SPI host 0 (passthrough) transmissions are correct ([test] Add spi_passthrough support to the power virus test #17747)
check SPI host 1 (non-passthrough) transmissions are correct ([test] Add spi_host1 DVsim support to power virus test #17707)
verify blocks (in task 3) are all active at the same time while the GPIO indicator pin is high ([test] Add DVsim support for the activity-checking part of power virus test #17800)

This adds the boilerplate code for the power virus test to partially address lowRISC#14814. Since this test will be rather large/complex, it will be committed in pieces over time. This initial commit contains a basic test checklist (that will be added-to/improved over time) and basic configurations for the pinmux, gpio, and adc_ctrl peripherals. Signed-off-by: Timothy Trippel <[email protected]>

This adds the boilerplate code for the power virus test to partially address #14814. Since this test will be rather large/complex, it will be committed in pieces over time. This initial commit contains a basic test checklist (that will be added-to/improved over time) and basic configurations for the pinmux, gpio, and adc_ctrl peripherals. Signed-off-by: Timothy Trippel <[email protected]>

tjaychen · 2022-11-13T23:28:39Z

@timothytrippel @arunthomas based on what we discussed, we're going to lower the priority of this test to M3 and also V3 (so it doesn't pop up on the dashboard).

Let me know if you disagree.

Previously, only a blocking version of the `rsa_3072_verify` function existed. For the power virus test (see lowRISC#14814), however, we want the ability to initiate OTBN operations, and then free up the CPU to complete other tasks. This adds a non-blocking version of the `rsa_3072_verify` function to the crypto library to support this use case. Signed-off-by: Timothy Trippel <[email protected]>

Previously, only a blocking version of the `rsa_3072_verify` function existed. For the power virus test (see #14814), however, we want the ability to initiate OTBN operations, and then free up the CPU to complete other tasks. This adds a non-blocking version of the `rsa_3072_verify` function to the crypto library to support this use case. Signed-off-by: Timothy Trippel <[email protected]>

This updates the power virus test to: 1. activate the entropy complex during the max power epoch, 2. toggle the GPIO max power indicator pin using `mmio_write_*` function directly, rather than using the DIFs, which are too slow, and 3. check the AES status by polling the CSR directly, rather the using the DIFs (for same reason as in 2 above). This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel · 2023-03-02T06:39:11Z

Making note here of potential future optimizations / areas of investigation. These are not immediately required for this test, but may be revisited in later on.

driving usbdev
explore clock gating effects on power swings
triggering other memory controller operations? (OTP / SRAM operations)

This both: 1. updates the crypto operations (AES, HMAC, and KMAC) to enable checking their outputs against known outputs, and 2. checks the outputs of the crypto blocks (AES, HMAC, and KMAC) for correctness after exiting the max power epoch. This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

This updates the power virus test to: 1. activate the entropy complex during the max power epoch, 2. toggle the GPIO max power indicator pin using `mmio_write_*` function directly, rather than using the DIFs, which are too slow, and 3. check the AES status by polling the CSR directly, rather the using the DIFs (for same reason as in 2 above). This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

This updates the power virus test to: 1. activate the entropy complex during the max power epoch, 2. toggle the GPIO max power indicator pin using `mmio_write_*` function directly, rather than using the DIFs, which are too slow, and 3. check the AES status by polling the CSR directly, rather the using the DIFs (for same reason as in 2 above). This partially addresses #14814. Signed-off-by: Timothy Trippel <[email protected]>

This both: 1. updates the crypto operations (AES, HMAC, and KMAC) to enable checking their outputs against known outputs, and 2. checks the outputs of the crypto blocks (AES, HMAC, and KMAC) for correctness after exiting the max power epoch. This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

This both: 1. updates the crypto operations (AES, HMAC, and KMAC) to enable checking their outputs against known outputs, and 2. checks the outputs of the crypto blocks (AES, HMAC, and KMAC) for correctness after exiting the max power epoch. This partially addresses #14814. Signed-off-by: Timothy Trippel <[email protected]>

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

This partially addresses #14814. Signed-off-by: Timothy Trippel <[email protected]>

msfschaffner added the Component:ChipLevelTest Used to filter the chip-level test backlog label Sep 7, 2022

msfschaffner added this to the Project: M2 milestone Sep 7, 2022

timothytrippel mentioned this issue Oct 4, 2022

[top] Track system level test cases #14095

Closed

2 tasks

timothytrippel self-assigned this Oct 4, 2022

timothytrippel mentioned this issue Oct 25, 2022

[top-level,test] add initial power virus test boilerplate #15717

Merged

msfschaffner mentioned this issue Oct 28, 2022

[entropy_complex] Corner case tests at the chip level #10970

Closed

3 tasks

tjaychen modified the milestones: Project: M2, Project: M3 Nov 13, 2022

johngt mentioned this issue Nov 15, 2022

[chip-test] chip_sw_power_idle_load #14815

Closed

6 tasks

timothytrippel mentioned this issue Dec 8, 2022

[test] add entropy complex configuration to power virus test #16725

Merged

This was referenced Dec 17, 2022

[test] configure crypto blocks in power virus test #16886

Merged

[test] configure UARTs and I2Cs in power virus test #16923

Merged

timothytrippel mentioned this issue Feb 8, 2023

[test] drive SPI host 1 in power virus test #17248

Merged

timothytrippel mentioned this issue Feb 8, 2023

[crypto] add non-blocking rsa_3072_verify function #17254

Merged

bilgiday self-assigned this Feb 9, 2023

moidx modified the milestones: Discrete: M3, Discrete: M2.5 Feb 15, 2023

timothytrippel mentioned this issue Feb 15, 2023

[test] exercise OTBN in power virus test #17284

Merged

timothytrippel mentioned this issue Feb 27, 2023

[flash_ctrl] Backdoor loading enhancements #9322

Closed

timothytrippel mentioned this issue Mar 2, 2023

[test] optimize max power epoch in power virus test #17410

Merged

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 14, 2023

[test] enable flash scrambling/ECC in power virus test

bcba111

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 14, 2023

[test] enable flash scrambling/ECC in power virus test

dda6e9a

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 15, 2023

[test] enable flash scrambling/ECC in power virus test

c80a78e

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 15, 2023

[test] enable flash scrambling/ECC in power virus test

5572eba

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 16, 2023

[test] enable flash scrambling/ECC in power virus test

fdd23f3

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 16, 2023

[test] enable flash scrambling/ECC in power virus test

fc068f1

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel mentioned this issue Mar 16, 2023

[util,test] fix bug in flash scrambling script and add flash scrambling smoketest #17575

Merged

timothytrippel added a commit to timothytrippel/opentitan that referenced this issue Mar 16, 2023

[test] enable flash scrambling/ECC in power virus test

6b944e7

This partially addresses lowRISC#14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel added a commit that referenced this issue Mar 16, 2023

[test] enable flash scrambling/ECC in power virus test

b6b5d81

This partially addresses #14814. Signed-off-by: Timothy Trippel <[email protected]>

timothytrippel linked a pull request Apr 4, 2023 that will close this issue

[test] Add DVsim support for the activity-checking part of power virus test #17800

Merged

timothytrippel closed this as completed in #17800 Apr 5, 2023

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[chip-test] chip_sw_power_max_load #14814

[chip-test] chip_sw_power_max_load #14814

msfschaffner commented Sep 7, 2022 •

edited by timothytrippel

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timothytrippel commented Oct 4, 2022

timothytrippel commented Oct 28, 2022 •

edited

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tjaychen commented Nov 13, 2022

timothytrippel commented Mar 2, 2023

[chip-test] chip_sw_power_max_load #14814

[chip-test] chip_sw_power_max_load #14814

Comments

msfschaffner commented Sep 7, 2022 • edited by timothytrippel Loading

Test point name

Host side component

OpenTitanTool infrastructure implemented

Contact person

Checklist

timothytrippel commented Oct 4, 2022

timothytrippel commented Oct 28, 2022 • edited Loading

Test Checklist (WIP):

(Task 0) Main:

(Task 1) Block Loading Operations:

(Task 2) Activate All Blocks and Check results

OTP Test Parameters:

Host Side (DV sequence) Test Component:

tjaychen commented Nov 13, 2022

timothytrippel commented Mar 2, 2023

msfschaffner commented Sep 7, 2022 •

edited by timothytrippel

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timothytrippel commented Oct 28, 2022 •

edited

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