[regtool] hwext register with rw1c fields results in partial implementation.

[shareefj]

Description

I've been trying to get regtool to output sensible RTL that uses an external register with swaccess of rw1c. When running the following HJSON through the tool, I get a reg_top.sv that tries to use a non-existent reg2hw.enable.re signal.

I'm working around this at the moment by burning registers duplicating the external ones.

{
  name: BLOCK
  cip_id: 1001
  version: 1.1.1
  regwidth: 32
  registers:
  [
    {
      skipto: 0x0
    }
    {
      name: ENABLE
      desc: ""
      hwext: "true"
      hwqe: "true"
      hwre: "true"
      
      fields:
      [
        {
          name: EN
          desc: ""
          bits: 0
          resval: 0
          hwaccess: hwo
          swaccess: rw1c
        }
      ]
    }
  ]
  clocking:
  [
    {
      clock: clk_i
      reset: rst_ni
      idle: idle
      primary: "true"
    }
  ]
  bus_interfaces:
  [
    {
      protocol: tlul
      direction: device
    }
  ]
}

The pkg file looks like:

package block_reg_pkg;

  // Address widths within the block
  parameter int BlockAw = 2;

  ////////////////////////////
  // Typedefs for registers //
  ////////////////////////////

  typedef struct packed {
    logic        d;
  } block_hw2reg_enable_reg_t;

  // HW -> register type
  typedef struct packed {
    block_hw2reg_enable_reg_t enable; // [0:0]
  } block_hw2reg_t;

  // Register offsets
  parameter logic [BlockAw-1:0] BLOCK_ENABLE_OFFSET = 2'h 0;

  // Reset values for hwext registers and their fields
  parameter logic [0:0] BLOCK_ENABLE_RESVAL = 1'h 0;
  parameter logic [0:0] BLOCK_ENABLE_EN_RESVAL = 1'h 0;

  // Register index
  typedef enum int {
    BLOCK_ENABLE
  } block_id_e;

  // Register width information to check illegal writes
  parameter logic [3:0] BLOCK_PERMIT [1] = '{
    4'b 0001  // index[0] BLOCK_ENABLE
  };

endpackage

and the snippet of the RTL top level looks like:

  // Register instances
  // R[enable]: V(True)
  logic enable_qe;
  logic [0:0] enable_flds_we;
  assign enable_qe = &enable_flds_we;
  prim_subreg_ext #(
    .DW    (1)
  ) u_enable (
    .re     (enable_re),
    .we     (enable_we),
    .wd     (enable_wd),
    .d      (hw2reg.enable.d),
    .qre    (reg2hw.enable.re),
    .qe     (enable_flds_we[0]),
    .q      (),
    .ds     (),
    .qs     (enable_qs)
  );

[shareefj]

Actually, it looks like I can work around this by making the hwaccess: hrw. The fields then magically appear in the pkg.

Is this what you intended? Should you be throwing an error here rather than outputting broken RTL or was this intended to be an option?

I was also trying this with swaccess: rc and that also has the same issue.

[rswarbrick]

To make sure I understand the problem:

• Your hjson specifies a register and asks for an hwre signal
• The generated reg_top tries to connect the prim_subreg_ext so that it writes to reg2hw.<REG_NAME>.re
• But the reg2hw structure doesn't have an re signal for that register.

Is that right? If so, I suspect we need to make a small tweak to the Python code that generates the package defining reg2hw.

If you want to debug further, you could poke around by locally adding edits to the reg_pkg.sv.tpl and trying to figure out what is getting included/skipped and why.

[shareefj]

@rswarbrick Exactly right. I'm assuming that those signals aren't templated unless the register has a hardware read interface. I'll see if I can do some poking.