[tlul] V2(S) Signoff

[msfschaffner]

Description

Ensure V2(S) signoff criteria are still maintained (this is not a focus area block).

[msfschaffner]

Commits since Earlgrey-ES tapeout

$ git rev-parse --short HEAD

9935a46

$ git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/tlul

698dcc3 [tlul] Choose valid default depths
2f8cd83 [tlul/rtl] Change ASSERT_I to ASSERT to fix erroneous assertion failure
7688e71 [reggen] Add initial support for version and cip_id hjson fields
fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
ff2314b [doc,report] Fix the dvsim report links to the testplans
0ba10b3 [reggen] Add CIP_IDs and bump all major versions
249bddb [chip,dv] update constraint with short_xbar_test
09a2f13 [chip,dv] add short iteration option to xbar test

Issues closed since the Earlgrey-ES tapeout

• [reggen] Supports only TLUL as bus protocol? #20303
  • community question, no RTL impact
• [sw] Sram uninitialized address are accessed when using execute from SRAM mode #20687
  • SW change, no RTL impact
• [edn/dv] add CSRNG command item to EDN DV env #19751
  • SW change, no RTL impact
• [dv] devmode related TODOs in DV #16739
  • devmode has been removed. this is a minor RTL change that is reflected in all generated reg_top modules and their instantiation. it does however not change behavior and the DV does not have to be updated, since we simply removed the mode that was never used so far.
• num_req_outstanding might overflow in tlul_socket_1n #10328
  • closed as not planned
• TLUL Error Response and devmode #10311
  • related to [dv] devmode related TODOs in DV #16739 and fixed by the same patch.

Currently open issues

• [regtool] hwext register with rw1c fields results in partial implementation. #19696
  • template bug in a corner case that is not relevant for Earlgrey PROD
• [tlul] sequence item constraints miss to create proper transactions. #19263
  • DV issue to be closed for V3
• [tlul] TL-UL data zeroing inconsistencies #17330
  • backlog issue, not required from a security standpoint (likely close as not planned)
• [tlul] Side-channel Hamming weight leakage of data on TL-UL #16767
  • no HW fix needed, needs to be captured in SW security guidelines
• [tlul] Consider refactoring tlul_adapter_reg #15822
  • nice to have refactoring issue, not planned for Earlgrey PROD
• [reggen] Error check for data-intg-passthrough #9544
  • enhancement for a corner case that is currently not used in the design. not needed for Earlgrey PROD.
• [tlul] tlul_sram_byte data integrity check #8815
  • likely no RTL change needed, needs to be captured in SW guidelines
• Document TLUL integrity #7953
  • triaged for documentation improvement milestone, should not be blocking
• [sram_ctrl] Consider refactoring tlul_adapter_sram #7462
  • nice to have refactoring issue, not planned for Earlgrey PROD
• [tlul] How PutFullData vs PutPartialData should be used #1867
  • enhancement that is not required for Earlgrey PROD

Coverage report from 02/18/2024

xbar_main

xbar_peri

Summary

The only fix that had RTL impact was the removal of devmode, which does not have DV impact since it was never used.
V2S coverage levels are still fulfilled in the XBAR testbenches and the adapter modules for TLUL are covered as part of the individual IPs where they are instantiated.

The IP therefore still fulfills V2S quality level ( unless we decide that needs an RTL fix #8815, which does not look likely at this point).

[msfschaffner]

@andreaskurth @GregAC @vogelpi can you PTAL?

[andreaskurth]

With the same conditions and analysis as for the D2(S) signoff review I did, I agree that tlul fulfills the V2S signoff criteria for this release.

[vogelpi]

I agree with @andreaskurth , this still fulfills V2S. Thanks for putting this together @msfschaffner !