[sram_ctrl] V2(S) Signoff

[msfschaffner]

Description

Ensure V2(S) signoff criteria are still maintained (this is not a focus area block).

[msfschaffner]

Commits since Earlgrey-ES tapeout

$ git rev-parse --short HEAD

2d82cc8

$ git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/sram_ctrl

be22ed7 [dv,sram_ctrl] Fix failing assertion
b5642fe [dv,sram_ctrl,otp_ctrl] Add some uvm_info messages and fix comment typos
29c97ad [dv,sram_ctrl] Fix key scramble with escalation
36c168c (tag: Earlgrey-PROD-M2-RC0) [dv,sram_ctrl] Fix a few test failures
5e6f05a [sram_ctrl] Minor alignment of init and key request behavior
62ef232 [dv,sram_ctrl] Improve detection of init_done and key_scr_valid
887ddfb [dv,sram_ctrl] Fix a few failing tests
532da60 [sram_ctrl/dv] Fix missing case in scoreboard
06bd802 [otp_ctrl] Add second HW_CFG partition
c721c51 [rtl, prim] Add 'commit' functionality to prim_count
61a237e [util/reggen] reverse order of substruct generation
c939d9a [otp_ctrl] Add support for multiple HW_CFG partitions
0aed4e7 [sram_ctrl] Add RW1C status for scr key rotation
38b32de [sram_ctrl] Bump version of the sram_ctrl
de31bdf [reggen] Remove the devmode input
803d9ae [prim, rom_ctrl] Remove S&P layer from data scrambling
7078872 [sram_ctrl,doc] List (testable) features of sram_ctrl
777e5ba [sram_ctrl,doc] Fix minor style problems in theory_of_operation.md
95d13cb [sram_ctrl,doc] Avoid a "double prince" in README.md
1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
59f8142 [doc] Moved badges over to using hosted images
735dfbf [doc] sram_ctrl registers and interfaces now use CMDGEN
a2be383 [dv/top-level] Fix sram data integrity error injection
7688e71 [reggen] Add initial support for version and cip_id hjson fields
fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
0ba10b3 [reggen] Add CIP_IDs and bump all major versions
d25b165 [sram_ctrl] Synchronize lc signals

Issues closed since the Earlgrey-ES tapeout

• [tlgen.py] ERROR: get_s1n_if_exist hits DEVICE type (unexpected) for node: flash_ctrl #19500
• [pwrmgr/sram_ctrl] Use synchronizers on all LC signals #19051
• [sram_ctrl] RW1C status bit for scrambling key rotation acknowledgement #18663
• [dv/cdc] Enable CDC instrumentation in all ips #16689
• [otbn] Check seed_valid bit of OTP scrambling interface #13201
• [sram_ctrl, flash_ctrl, icache, otbn] Protecting scrambling keys at rest #12111
• [entropy_complex] Corner case tests at the chip level #10970
• [sram_ctrl] Consider merging INIT with RENEW_SCR_KEY #9464

Currently open issues

• [rv_core_ibex,RAM] Setup violation from the RAMs #19782 -> partially addressed by S&P layer removal, future fixes will be done at system level outside SRAM_CTRL
• [chip-test] Move C tests without external host from tests/sim_dv/ to tests/ #16636 -> SW issue
• [dv] VCS UNR misses simple cases #14304 -> DV tooling issue
• [reggen] Add tooling for checking in-line countermeasure annotations #10071 -> does not affect SRAM_CTRL anymore
• [sram_ctrl] Consider refactoring tlul_adapter_sram #7462 -> future release
• [sw] polling in ROM #6220 -> SW issue

The only relevant open issue is #19782 which will be handled at the system level once a new timing report is available (removal of the S&P diffusion layer in memory scrambling was already done as a partial fix).

Coverage report from 03/17/2024

Main SRAM:

Retention SRAM:

Pass rates are all above 90% for V2S tests.

Summary

Changes since Earlgrey ES tapeout include misc reggen and doc fixes. The most notable changes that affect functionality are:

• addition of an RW1C status CSR for SCR key rotation [sram_ctrl] RW1C status bit for scrambling key rotation acknowledgement #18663
• removal of the S&P layer in the memory scrambling RFC: Removing the S&P Layer in Scrambling for Top Earl Grey #20788
• added synchronizers on multibit LC/MuBi input signals [pwrmgr/sram_ctrl] Use synchronizers on all LC signals #19051

These changes have been reflected in the docs and the DV has been updated accordingly and several patches have been made to improve the testbench. Coverage and pass rates are all above 90% for tests up to V2S level.

The block hence still fulfills V2S quality as claimed in the Hjson:

opentitan/hw/ip/sram_ctrl/data/sram_ctrl.hjson

Lines 20 to 24 in 1fb24e3

	version: "1.1.0",
	life_stage: "L1",
	design_stage: "D3",
	verification_stage: "V2S",
	dif_stage: "S2",

[msfschaffner]

@matutem @rswarbrick PTAL

[msfschaffner]

This should be good to go now, based on nightlies from the WE.

[matutem]

Agreed.