[edn/dv] Implement my V2 Review TODO Items listed in Issue #11489

hw/dv/sv/csrng_agent/csrng_agent.sv

@@ -33,6 +33,7 @@ class csrng_agent extends dv_base_agent #(
  cfg.m_cmd_push_agent_cfg.is_active = cfg.is_active;
  cfg.m_cmd_push_agent_cfg.agent_type = PushAgent;
  cfg.m_cmd_push_agent_cfg.if_mode = cfg.if_mode;
+ cfg.m_cmd_push_agent_cfg.zero_delays = cfg.cmd_ack_zero_delays;
 
  m_genbits_push_agent = push_pull_agent#(csrng_pkg::FIPS_GENBITS_BUS_WIDTH)::type_id::
  create("m_genbits_push_agent", this);

hw/dv/sv/csrng_agent/csrng_device_driver.sv

@@ -6,7 +6,8 @@ class csrng_device_driver extends csrng_driver;
  `uvm_component_utils(csrng_device_driver)
  `uvm_component_new
 
- rand uint cmd_ack_dly;
+ uint cmd_ack_dly;
+ bit rsp_sts;
 
  virtual task run_phase(uvm_phase phase);
  // base class forks off reset_signals() and get_and_drive() tasks
@@ -29,7 +30,8 @@ class csrng_device_driver extends csrng_driver;
  cmd_ack_dly, cmd_ack_dly inside {cfg.min_cmd_ack_dly, cfg.max_cmd_ack_dly};)
  repeat(cmd_ack_dly) @(cfg.vif.device_cb);
  cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_ack <= 1'b1;
- cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= 1'b0;
+ `DV_CHECK_STD_RANDOMIZE_FATAL(rsp_sts)
+ cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= rsp_sts;
  @(cfg.vif.device_cb);
  cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_ack <= 1'b0;
  cfg.vif.device_cb.cmd_rsp_int.csrng_rsp_sts <= 1'b0;

hw/dv/sv/csrng_agent/csrng_if.sv

@@ -67,7 +67,6 @@ interface csrng_if (input clk, input rst_n);
  task automatic wait_cmd_ack();
  do @(mon_cb);
  while (!mon_cb.cmd_rsp.csrng_rsp_ack);
- `DV_CHECK_FATAL(mon_cb.cmd_rsp.csrng_rsp_sts == '0, , "csrng_if")
  endtask
 
 endinterface

hw/dv/sv/csrng_agent/csrng_monitor.sv

@@ -14,6 +14,9 @@ class csrng_monitor extends dv_base_monitor #(
  // csrng_agent_cov: cov
  // uvm_analysis_port #(csrng_item): analysis_port
 
+ // Analysis port for the csrng_rsp_sts.
+ uvm_analysis_port #(bit) rsp_sts_ap;
+
  uvm_tlm_analysis_fifo#(push_pull_item#(.HostDataWidth(csrng_pkg::CSRNG_CMD_WIDTH)))
  csrng_cmd_fifo;
 
@@ -25,6 +28,7 @@ class csrng_monitor extends dv_base_monitor #(
  super.build_phase(phase);
 
  csrng_cmd_fifo = new("csrng_cmd_fifo", this);
+ rsp_sts_ap = new("rsp_sts_ap", this);
  endfunction
 
  task run_phase(uvm_phase phase);
@@ -125,6 +129,7 @@ class csrng_monitor extends dv_base_monitor #(
  // detecting another request, as this is not a pipelined protocol.
  `DV_SPINWAIT_EXIT(while (!cfg.vif.mon_cb.cmd_rsp.csrng_rsp_ack) @(cfg.vif.mon_cb);,
  wait(in_reset))
+ rsp_sts_ap.write(cfg.vif.cmd_rsp.csrng_rsp_sts);
  end
  end
  endtask

hw/dv/sv/csrng_agent/seq_lib/csrng_device_seq.sv

@@ -19,7 +19,6 @@ class csrng_device_seq extends csrng_base_seq;
 
  p_sequencer.req_analysis_fifo.get(req);
  `uvm_info(`gfn, $sformatf("Received item: %s", req.convert2string()), UVM_HIGH)
- cfg.m_cmd_push_agent_cfg.zero_delays = cfg.cmd_ack_zero_delays;
  if (req.acmd == csrng_pkg::GEN) begin
  m_genbits_seq = push_pull_host_seq#(csrng_pkg::FIPS_GENBITS_BUS_WIDTH)::type_id::
  create("m_genbits_seq");

hw/ip/edn/data/edn_testplan.hjson

@@ -113,7 +113,7 @@ covergroups: [
  '''
  }
  {
- name: cs_commands_cg
+ name: cs_cmds_cg
  desc: '''
  Covers the following:
  - csrng_commands vs clen, flags, glen
@@ -122,12 +122,6 @@ covergroups: [
  Crosses between above coverpoints
  '''
  }
- {
- name: edn_genbits_cg
- desc: '''
- Covers genbits requested/returned delays
- '''
- }
  {
  name: err_test_cg
  desc: '''

hw/ip/edn/dv/env/edn_env.sv

@@ -60,6 +60,9 @@ class edn_env extends cip_base_env #(
  m_endpoint_agent[i].monitor.analysis_port.connect
  (scoreboard.endpoint_fifo[i].analysis_export);
  end
+
+ m_csrng_agent.monitor.rsp_sts_ap.connect
+ (scoreboard.rsp_sts_fifo.analysis_export);
  end
 
  for (int i = 0; i < cfg.num_endpoints; i++) begin

hw/ip/edn/dv/env/edn_scoreboard.sv

@@ -18,6 +18,7 @@ class edn_scoreboard extends cip_base_scoreboard #(
  genbits_fifo;
  uvm_tlm_analysis_fifo#(push_pull_item#(.HostDataWidth(FIPS_ENDPOINT_BUS_WIDTH)))
  endpoint_fifo[MAX_NUM_ENDPOINTS];
+ uvm_tlm_analysis_fifo#(bit) rsp_sts_fifo;
 
  // local queues to hold incoming packets pending comparison
  bit[FIPS_ENDPOINT_BUS_WIDTH - 1:0] endpoint_data_q[$];
@@ -29,6 +30,7 @@ class edn_scoreboard extends cip_base_scoreboard #(
 
  genbits_fifo = new("genbits_fifo", this);
  cs_cmd_fifo = new("cs_cmd_fifo", this);
+ rsp_sts_fifo = new("cs_rsp_sts_fifo", this);
 
  for (int i = 0; i < cfg.num_endpoints; i++) begin
  endpoint_fifo[i] = new($sformatf("endpoint_fifo[%0d]", i), this);
@@ -48,6 +50,7 @@ class edn_scoreboard extends cip_base_scoreboard #(
 
  fork
  process_genbits_fifo();
+ process_rsp_sts_fifo();
  join_none
 
  for (int i = 0; i < cfg.num_endpoints; i++) begin
@@ -151,6 +154,18 @@ class edn_scoreboard extends cip_base_scoreboard #(
  end
  endtask
 
+ task process_rsp_sts_fifo();
+ bit rsp_sts;
+
+ forever begin
+ rsp_sts_fifo.get(rsp_sts);
+ if ((cfg.boot_req_mode == MuBi4False) && (cfg.auto_req_mode == MuBi4False)) begin
+ // Check register value if not boot_req_mode/auto_req_mode
+ csr_spinwait(.ptr(ral.sw_cmd_sts.cmd_sts), .exp_data(rsp_sts));
+ end
+ end
+ endtask
+
  task process_endpoint_fifo(uint endpoint);
  push_pull_item#(.HostDataWidth(FIPS_ENDPOINT_BUS_WIDTH)) endpoint_item;
  uint index, q_size;