As7312 54x add sfp rest and fan policy

device/accton/x86_64-accton_as7312_54x-r0/plugins/sfputil.py

@@ -26,10 +26,10 @@ class SfpUtil(SfpUtilBase):
 
  _port_to_eeprom_mapping = {}
  _cpld_mapping = {
-  0: "4-0060",
-  1: "5-0062",
-  2: "6-0064",
- } 
+  0: "4-0060",
+  1: "5-0062",
+  2: "6-0064",
+ }
  _port_to_i2c_mapping = {
  0: 18, 
  1: 19, 
@@ -137,29 +137,40 @@ def __init__(self):
 
  SfpUtilBase.__init__(self)
 
+
+ # For port 48~51 are QSFP, here presumed they're all split to 4 lanes.
+ def get_cage_num(self, port_num): 
+ cage_num = port_num
+ if (port_num >= self.QSFP_PORT_START):
+ cage_num = (port_num - self.QSFP_PORT_START)/4
+ cage_num = cage_num + self.QSFP_PORT_START
+
+ return cage_num
+
+ # For cage 0~23 and 48~51 are at cpld2, others are at cpld3.
+ def get_cpld_num(self, port_num): 
+ cpld_i = 1
+ cage_num = self.get_cage_num(port_num)
+ if (port_num > 23 and port_num < self.QSFP_PORT_START):
+ cpld_i = 2
+
+ if (cage_num >= 52): 
+ cpld_i = 2
+
+ return cpld_i
+
  def get_presence(self, port_num):
  # Check for invalid port_num
  if port_num < self.port_start or port_num > self.port_end:
  return False
 
- # For cage 0~23 and 48~51 are at cpld2, others are at cpld3.
- # For port 48~51 are QSFP, here presumed they are all broken-out to 4 lanes.
- cage_num = port_num 
- cpld_i = 1 
- if (port_num > 23):
- cpld_i = 2
-
- if (port_num >= self.QSFP_PORT_START):
- cpld_i = 1 
- cage_num = (port_num - self.QSFP_PORT_START)/4
- cage_num = cage_num + self.QSFP_PORT_START
- if (cage_num >= 52): 
- cpld_i = 2
+ cage_num = self.get_cage_num(port_num)
+ cpld_i = self.get_cpld_num(port_num)
 
  cpld_ps = self._cpld_mapping[cpld_i]
  path = "/sys/bus/i2c/devices/{0}/module_present_{1}"
  port_ps = path.format(cpld_ps, cage_num+1)
- 
+
  try:
  val_file = open(port_ps)
  except IOError as e:
@@ -185,16 +196,18 @@ def reset(self, port_num):
  if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
  return False
 
-
- path = "/sys/bus/i2c/devices/5-0062/module_reset_{0}"
- port_ps = path.format(port_num+1)
+ cage_num = self.get_cage_num(port_num)
+ cpld_i = self.get_cpld_num(port_num)
+ cpld_ps = self._cpld_mapping[cpld_i]
+ path = "/sys/bus/i2c/devices/{0}/module_reset_{1}"
+ port_ps = path.format(cpld_ps, cage_num+1)
  try:
  reg_file = open(port_ps, 'w')
  except IOError as e:
  print "Error: unable to open file: %s" % str(e) 
  return False
 
- reg_value = '1'
+ reg_value = '0'
 
  reg_file.write(reg_value)
  reg_file.close()