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soc: arm: cypress: psoc6: Add Cortex-M0+ interrupt mux support #29459

Merged
merged 3 commits into from
Jan 20, 2021
Merged

soc: arm: cypress: psoc6: Add Cortex-M0+ interrupt mux support #29459

merged 3 commits into from
Jan 20, 2021

Commits on Jan 20, 2021

  1. soc: arm: cypress: psoc6: Update soc.h includes 

    Update <soc.h> include files.  This removes the unnecessary
<kernel_includes.h> file.  In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.

Signed-off-by: Gerson Fernando Budke <[email protected]>
    @nandojve
    nandojve committed Jan 20, 2021
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  2. dts: arm: cypress: psoc6: Drop nvic reference 

    The psoc6.dtsi file declare a reference to nvic.  Since it was proper
defined at psoc6_cm0/4.dtsi files this entry is redundant.  Drop the
useless entry.

Signed-off-by: Gerson Fernando Budke <[email protected]>
    @nandojve
    nandojve committed Jan 20, 2021
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  3. soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support 

    PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU.  It uses
a multiplex before any NVIC interrupt line.  The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.

Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.

Signed-off-by: Gerson Fernando Budke <[email protected]>
    @nandojve
    nandojve committed Jan 20, 2021
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