soc: arm: cypress: psoc6: Add Cortex-M0+ interrupt mux support

[nandojve]

PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The minimal support was added to allow interrupts be available for both CPUs.

Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated.

This update <soc.h> include files removing the unnecessary <kernel_includes.h> file. In addition, add <sys/util.h> to expose macros and <devicetree.h> following general standards.

This solves #28442 and allows development of drivers that can be shared between SoC cores including, external interrupts by GPIO, serial, spi etc.

[nandojve]

Rebase and add missing map-nvic documentation.

[galak]

Need to look at this in more detail. Wondering how this compares to what we have for rv32m1_vega

[nandojve]

Need to look at this in more detail. Wondering how this compares to what we have for rv32m1_vega

I know this is an intermediate solution. At drivers, the work was done on the macro that connects IRQ and it was defined externally for an rebase, if necessary. @mbolivar already told me about rv32m1_vega but I didn't see how user define the interrupt on DT, Cy m0 problem.

What I think it will be easy to user is described at #28442 but I face the constfy problem with DT_INST_FOREACH_CHILD.

[mbolivar-nordic]

I didn't see how user define the interrupt on DT, Cy m0 problem.

I don't understand "Cy m0 problem", sorry.

Perhaps this is a chance to clean up the devicetree documentation (and maybe implementation) with regards to multi-level interrupts, but can you explain what you tried when you tried to make intermediate interrupt controller nodes for the interrupt mux? The idea is to set the interrupt-parent to point to those and to use the normal interrupts property to specify interrupts in DT. Can you explain what didn't work the way you expected when you tried that?

[nandojve]

I didn't see how user define the interrupt on DT, Cy m0 problem.

I don't understand "Cy m0 problem", sorry.

Perhaps this is a chance to clean up the devicetree documentation (and maybe implementation) with regards to multi-level interrupts, but can you explain what you tried when you tried to make intermediate interrupt controller nodes for the interrupt mux? The idea is to set the interrupt-parent to point to those and to use the normal interrupts property to specify interrupts in DT. Can you explain what didn't work the way you expected when you tried that?

I think I understand my difficult, for some reason I didn't look at some file on rv32m1_vega dts directory. That create a gap that I wasn't understand how to fill. I hope this update is close to what I rely need to do.
Thanks!

[mbolivar-nordic]

This looks nice to me! Just a couple of minor questions but I think this seems sane.

[nandojve]

rebase

[nandojve]

Hello @galak !
I was wondering if there is anything missing here?

[ADEscobar]

Is this ready to be merged then?

[mbolivar-nordic]

Is this ready to be merged then?

No, it needs another +1, ideally from @galak

[galak]

• Change #size-cells to 1 for mux registers. Even if size is just 1, since these are still MMIO registers.
• Add some comments on what / how the mux values are figured out. Seen inline.

[galak]

Some minor tweaks, and on general question if we should just remove status="disabled" for the "cypress,psoc6-intmux-ch" nodes. Means one less thing the board dts file would have to modify.

[galak]

One other nit: can you see if we can remove label. Want to phase it out in the future and I don't think you need it at all.

[nandojve]

One other nit: can you see if we can remove label. Want to phase it out in the future and I don't think you need it at all.

Yes, I removed and tested with GPIO driver which depends on this.