linker: aarch32: simplify memory region generation

dts/arm/st/wb/stm32wb.dtsi

@@ -31,6 +31,16 @@
  compatible = "mmio-sram";
  };
 
+ sram1: memory@20030000 {
+ compatible = "mmio-sram";
+ reg = <0x20030000 0x2800>;
+ };
+
+ sram2: memory@20038000 {
+ compatible = "mmio-sram";
+ reg = <0x20038000 0x5000>;
+ };
+
  soc {
  flash: flash-controller@58004000 {
  compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";

dts/arm/ti/cc1352r.dtsi

@@ -14,5 +14,17 @@
 
  flash0: serial-flash@0 {
  reg = <0x0 DT_SIZE_K(352)>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* CCFG registers occupy the last 88 bytes of flash */
+ ti_ccfg_partition: partition@57fa8 {
+ label = "ti_ccfg";
+ reg = <0x57fa8 88>;
+ };
+ };
  };
 };

dts/arm/ti/cc2652r.dtsi

@@ -14,5 +14,17 @@
 
  flash0: serial-flash@0 {
  reg = <0x0 DT_SIZE_K(352)>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* CCFG registers occupy the last 88 bytes of flash */
+ ti_ccfg_partition: partition@57fa8 {
+ label = "ti_ccfg";
+ reg = <0x57fa8 88>;
+ };
+ };
  };
 };

include/arch/arm/aarch32/cortex_m/scripts/linker.ld

@@ -15,6 +15,7 @@
 #include <linker/sections.h>
 #include <devicetree.h>
 
+#include <linker/devicetree_regions.h>
 #include <linker/linker-defs.h>
 #include <linker/linker-tool.h>
 
@@ -39,18 +40,11 @@
 #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
 #endif
 
-#ifdef CONFIG_HAS_TI_CCFG
-#define CCFG_SIZE 88
-#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \
- CCFG_SIZE)
-#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)
-#else
 #if CONFIG_FLASH_LOAD_SIZE > 0
 #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
 #else
 #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
 #endif
-#endif
 
 #if defined(CONFIG_XIP)
 #if defined(CONFIG_IS_BOOTLOADER)
@@ -66,21 +60,6 @@
 #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
-#define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))
-#define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm))
-#endif
-
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
-#define ITCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))
-#define ITCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
-#endif
-
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
-#define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
-#define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
-#endif
-
 #if defined(CONFIG_CUSTOM_SECTION_ALIGN)
 _region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;
 #else
@@ -107,34 +86,21 @@ _region_min_align = 4;
 MEMORY
  {
  FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
-#ifdef CONFIG_HAS_TI_CCFG
- FLASH_CCFG (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE
-#endif
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
- CCM (rw) : ORIGIN = CCM_ADDR, LENGTH = CCM_SIZE
-#endif
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
- ITCM (rw) : ORIGIN = ITCM_ADDR, LENGTH = ITCM_SIZE
-#endif
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
- DTCM (rw) : ORIGIN = DTCM_ADDR, LENGTH = DTCM_SIZE
-#endif
  SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
-#ifdef CONFIG_BT_STM32_IPM
- SRAM1 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE
- SRAM2 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE
-#endif
-#ifdef CONFIG_MEMC_STM32_SDRAM
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)
- SDRAM1 (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram1)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram1))
-#endif
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
- SDRAM2 (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram2)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram2))
-#endif
-#endif
-#ifdef CONFIG_STM32_BACKUP_SRAM
- BACKUP_SRAM (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(backup_sram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(backup_sram))
-#endif
+ /* TI CCFG Registers */
+ DT_REGION_FROM_NODE_STATUS_OKAY(FLASH_CCFG, rwx, DT_NODELABEL(ti_ccfg_partition))
+ /* Data & Instruction Tightly Coupled Memory */
+ DT_REGION_FROM_NODE_STATUS_OKAY(ITCM, rw, DT_CHOSEN(zephyr_itcm))
+ DT_REGION_FROM_NODE_STATUS_OKAY(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
+ /* STM32 Core Coupled Memory */
+ DT_REGION_FROM_NODE_STATUS_OKAY(CCM, rw, DT_CHOSEN(zephyr_ccm))
+ /* STM32WB IPC RAM */
+ DT_REGION_FROM_NODE_STATUS_OKAY(SRAM1, rw, DT_NODELABEL(sram1))
+ DT_REGION_FROM_NODE_STATUS_OKAY(SRAM2, rw, DT_NODELABEL(sram2))
+ /* STM32 alternate RAM configurations */
+ DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM1, rw, DT_NODELABEL(sdram1))
+ DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM2, rw, DT_NODELABEL(sdram2))
+ DT_REGION_FROM_NODE_STATUS_OKAY(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))
  /* Used by and documented in include/linker/intlist.ld */
  IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
  }
@@ -266,14 +232,6 @@ SECTIONS
 
  GROUP_END(ROMABLE_REGION)
 
-/* Some TI SoCs have a special configuration footer, at the end of flash. */
-#ifdef CONFIG_HAS_TI_CCFG
- SECTION_PROLOGUE(.ti_ccfg,,)
- {
- KEEP(*(_TI_CCFG_SECTION_NAME))
- } > FLASH_CCFG
-#endif
-
  /*
  * These are here according to 'arm-zephyr-elf-ld --verbose',
  * before data section.

include/linker/devicetree_regions.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021, Commonwealth Scientific and Industrial Research
+ * Organisation (CSIRO) ABN 41 687 119 230.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generate memory regions from devicetree nodes.
+ */
+
+/* Declare a memory region */
+#define _REGION_DECLARE(name, attr, node) name(attr) : \
+ ORIGIN = DT_REG_ADDR(node), \
+ LENGTH = DT_REG_SIZE(node)
+
+/**
+ * @brief Generate a linker memory region from a devicetree node
+ *
+ * @param name name of the generated memory region
+ * @param attr region attributes to use (rx, rw, ...)
+ * @param node devicetree node with a <reg> property defining region location
+ * and size.
+ */
+#define DT_REGION_FROM_NODE_STATUS_OKAY(name, attr, node) \
+ COND_CODE_1(DT_NODE_HAS_STATUS(node, okay), \
+ (_REGION_DECLARE(name, attr, node)), \
+ ())

soc/arm/st_stm32/stm32wb/linker.ld

@@ -6,9 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define RAM1_SIZE (10 * 1K)
-#define RAM1_ADDR 0x20030000
-#define RAM2_SIZE (20 * 1K)
-#define RAM2_ADDR 0x20038000
-
 #include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt

@@ -7,3 +7,5 @@ zephyr_sources(ccfg.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c)
+
+zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld)

soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Commonwealth Scientific and Industrial Research
+ * Organisation (CSIRO) ABN 41 687 119 230.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+GROUP_START(FLASH_CCFG)
+
+SECTION_PROLOGUE(.ti_ccfg,,)
+{
+ KEEP(*(_TI_CCFG_SECTION_NAME))
+} GROUP_LINK_IN(FLASH_CCFG)
+
+GROUP_END(FLASH_CCFG)