Dev msft 20230710

.github/workflows/interactive-debugging.yml

@@ -18,7 +18,7 @@ jobs:
  CARGO_INCREMENTAL: 0
  SCCACHE_VERSION: 0.3.3
  # TODO: To update to 5.006, clean up lint errors
- VERILATOR_VERSION: v5.002
+ VERILATOR_VERSION: v5.012
  SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
  SCCACHE_GHA_CACHE_FROM: sccache-verilator-
  # Change this to a new random value if you suspect the cache is corrupted

Release_Notes.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/06/08*_
+_*Last Update: 2023/07/10*_
 
 ## Rev 0p8 ##
 

src/aes/config/aes.vf

@@ -1,10 +1,15 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
-+incdir+${CALIPTRA_ROOT}/src/aes/rtl
 +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/aes/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
 ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
@@ -16,23 +21,23 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
@@ -41,6 +46,7 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
@@ -61,6 +67,9 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv

src/aes/config/aes_pkg.vf

@@ -1,6 +1,72 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv

src/aes/config/compile.yml

@@ -3,7 +3,7 @@ provides: [aes_pkg]
 schema_version: 2.4.0
 requires:
  - edn_pkg
- - prim
+ - caliptra_prim
 targets:
  rtl:
  directories: [$COMPILE_ROOT/rtl]

src/ahb_lite_bus/config/ahb_lite_bus.vf

@@ -1,4 +1,18 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv

src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv

@@ -21,7 +21,8 @@
 
 module ahb_lite_2to1_mux #(
  parameter AHB_LITE_ADDR_WIDTH = 32,
- parameter AHB_LITE_DATA_WIDTH = 32
+ parameter AHB_LITE_DATA_WIDTH = 32,
+ parameter AHB_NO_OPT = 0
 ) (
  // ---------------------------------------
  // Global clock/reset
@@ -123,8 +124,8 @@ always_ff @(posedge hclk or negedge hreset_n) begin
  initiator1_pend_hwrite <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hwrite_i_1 : initiator1_pend_hwrite;
 
  //Capture pending address phase when initiators collide
- initiator0_pend_addr_ph <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator0_gnt;
- initiator1_pend_addr_ph <= (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator1_gnt; 
+ initiator0_pend_addr_ph <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~(hreadyout_i & initiator0_gnt);
+ initiator1_pend_addr_ph <= (initiator1_address_ph | initiator1_pend_addr_ph) & ~(hreadyout_i & initiator1_gnt); 
 
  //Transition to data phase when endpoint accepts address phase, hold when not ready
  initiator0_data_ph <= (initiator0_gnt) | (initiator0_data_ph & ~hreadyout_i);
@@ -143,12 +144,29 @@ always_comb initiator1_hsize = initiator1_pend_addr_ph ? initiator1_pend_hsize :
 always_comb initiator1_hwrite = initiator1_pend_addr_ph ? initiator1_pend_hwrite : hwrite_i_1;
 
 //Select the appropriate initiator
-//Initiator 0 gets priority
-//Stall the grant if initiator 1 is processing a data phase and address phase b2b
-always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & hreadyout_i;
-
-//Initiator 1 gets through only if initiator 0 isn't getting granted
-always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & hreadyout_i & ~initiator0_gnt;
+generate
+ if (AHB_NO_OPT) begin
+ //no optimization, data phase must complete before driving new address phase
+ //Initiator 0 gets priority
+ //Stall the grant only if initiator 1 is on its data phase
+ always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator1_data_ph;
+
+ //Initiator 1 gets through only if initiator 0 address phase isn't getting gnt, or in data phase
+ always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_data_ph & ~initiator0_gnt;
+ end else begin
+ //optimized to allow addr phase to overlap data phase, assumes no stalls
+ //Initiator 0 gets priority
+ //Stall the grant if initiator 1 is processing a data phase and address phase b2b
+ always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph);
+
+ //Initiator 1 gets through only if initiator 0 isn't getting granted
+ always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_gnt;
+
+ //optimized path doesn't look at stall
+ //only time this stalls is on error condition
+ `CALIPTRA_ASSERT_NEVER(ERR_2TO1MUX_STALL, ~hreadyout_i & (hresp_i == 1'b0), hclk, hreset_n)
+ end
+endgenerate
 
 //Mux the appropriate initiator and send out
 //Keep driving initiator 1 controls on data phase if init0 isn't getting a grant in that cycle

src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv

@@ -56,8 +56,10 @@ module ahb_lite_address_decoder #(
  output logic [NUM_RESPONDERS-1:0][1:0] htrans_o,
  output logic [NUM_RESPONDERS-1:0][2:0] hsize_o,
 
+ input logic force_bus_idle,
+
  // ----------------------------------------------
- // Respnder Disable
+ // Responder Disable
  // ----------------------------------------------
  input logic [NUM_RESPONDERS-1:0] responder_disable_i,
  output logic [NUM_RESPONDERS-1:0] access_blocked_o,
@@ -78,19 +80,23 @@ module ahb_lite_address_decoder #(
  logic [NUM_RESPONDERS-1:0] pending_hsel;
  logic hinitiator_ready_default;
  logic hinitiator_ready_int;
+ logic hinitiator_ready_int_q;
  logic [NUM_RESPONDERS-1:0] hsel_o_int_pre;
  logic [NUM_RESPONDERS-1:0] hsel_blocked;
  logic [NUM_RESPONDERS-1:0] hsel_o_int;
  logic hresp_error;
  logic hresp_error_r;
 
+ logic [1:0] htrans_q;
+
 
+ always_comb htrans_q = force_bus_idle ? AHB_XFER_IDLE : htrans_i;
 
  // Decode the address to appropriate Responder HSEL
  genvar resp_num;
  generate
  for (resp_num = 0; resp_num < NUM_RESPONDERS; resp_num++) begin: gen_responder_hsel
- assign hsel_o_int_pre[resp_num] = (haddr_i >= responder_start_addr_i[resp_num]) && (haddr_i <= responder_end_addr_i[resp_num]);
+ assign hsel_o_int_pre[resp_num] = ~force_bus_idle && (haddr_i >= responder_start_addr_i[resp_num]) && (haddr_i <= responder_end_addr_i[resp_num]);
  assign hsel_blocked [resp_num] = hsel_o_int_pre[resp_num] && responder_disable_i[resp_num];
  assign hsel_o_int [resp_num] = hsel_o_int_pre[resp_num] && !responder_disable_i[resp_num];
  end
@@ -100,7 +106,7 @@ module ahb_lite_address_decoder #(
  always @(posedge hclk or negedge hreset_n) begin
  if (!hreset_n)
  access_blocked_o <= '0;
- else if (|htrans_i && hinitiator_ready_int && |hsel_blocked)
+ else if (|htrans_q && hinitiator_ready_int_q && |hsel_blocked)
  access_blocked_o <= hsel_blocked;
  else
  access_blocked_o <= '0;
@@ -109,16 +115,16 @@ module ahb_lite_address_decoder #(
  always @(posedge hclk or negedge hreset_n) begin
  if (!hreset_n)
  pending_hsel <= '0;
- else if (|htrans_i && hinitiator_ready_int)
+ else if (|htrans_q && hinitiator_ready_int_q)
  pending_hsel <= hsel_o_int;
- else if (hinitiator_ready_int)
+ else if (hinitiator_ready_int_q)
  pending_hsel <= '0;
  end
 
  always_comb begin
  // Only flag errors for NONSEQ or SEQ type transfers
  // (BUSY transfers require OKAY response)
- hresp_error = htrans_i inside {AHB_XFER_NONSEQ, AHB_XFER_SEQ} && hinitiator_ready_int && ~|hsel_o_int;
+ hresp_error = htrans_q inside {AHB_XFER_NONSEQ, AHB_XFER_SEQ} && hinitiator_ready_int_q && ~|hsel_o_int;
  end
 
  always @(posedge hclk or negedge hreset_n) begin
@@ -133,18 +139,19 @@ module ahb_lite_address_decoder #(
  hresp_error_r <= 1'b0;
  else if (hresp_error)
  hresp_error_r <= 1'b1;
- else if (hinitiator_ready_int)
+ else if (hinitiator_ready_int_q)
  hresp_error_r <= 1'b0;
  else
  hresp_error_r <= hresp_error_r;
  end
 
  // Drive the address phase of the AHB Lite Transaction
+ // For RDC force ready signal when we force the bus idle
  always_comb begin
  for (int rr = 0; rr < NUM_RESPONDERS; rr++) begin
- hresponderready_o[rr] = hinitiator_ready_int;
+ hresponderready_o[rr] = hinitiator_ready_int_q;
  hwrite_o[rr] = hwrite_i;
- htrans_o[rr] = htrans_i;
+ htrans_o[rr] = htrans_q;
  hsize_o[rr] = hsize_i;
  haddr_o[rr] = haddr_i;
  hwdata_o[rr] = hwdata_i;
@@ -171,10 +178,11 @@ module ahb_lite_address_decoder #(
  hinitiator_ready_int = hreadyout_i[rr];
  end
  end
+ hinitiator_ready_int_q = hinitiator_ready_int | force_bus_idle;
  end
 
  assign hsel_o = hsel_o_int;
- assign hinitiatorready_o = hinitiator_ready_int;
+ assign hinitiatorready_o = hinitiator_ready_int_q;
 
 //Coverage
 `ifndef VERILATOR

src/ahb_lite_bus/rtl/ahb_lite_bus.sv

@@ -45,10 +45,15 @@ module ahb_lite_bus #(
  output logic [NUM_RESPONDERS-1:0] ahb_lite_resp_access_blocked_o,
 
  // ----------------------------------------------
- // Respnder Address Map (Start and End addresses)
+ // Responder Address Map (Start and End addresses)
  // ----------------------------------------------
  input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_start_addr_i,
- input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_end_addr_i
+ input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_end_addr_i,
+
+ // ----------------------------------------------
+ // Force bus idle during uc reset to prevent RDC violations
+ // ----------------------------------------------
+ input logic force_bus_idle
 );
 
  logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] haddr;
@@ -125,8 +130,10 @@ module ahb_lite_bus #(
  .htrans_o (htrans),
  .hsize_o (hsize),
 
+ .force_bus_idle (force_bus_idle),
+
  // ----------------------------------------------
- // Respnder Disable
+ // Responder Disable
  // ----------------------------------------------
  .responder_disable_i (ahb_lite_resp_disable_i),
  .access_blocked_o (ahb_lite_resp_access_blocked_o),