Dev msft 20230710 #149

anjpar · 2023-07-11T00:47:40Z

This PR includes the following updates:

Updated timestamp of README.md
Updated timestamp of Release_Notes.md
Merged PR 113668: RDC clock gating fix for warm reset and masking for fw update reset
Merged PR 114956: Clock gating tests for mbox, DOE and KV, related bug fixes, coverage updates
Merged PR 114014: [UVM] Mailbox testcases for invalid behavior
Merged PR 114429: Merge dev-msft into MSFT internal repo
Merged PR 114881: UVM mailbox sequence fix for invalid PAUSER access check
Merged PR 114587: New soc_ifc register tests, special cases including interrupt block registers
Merged PR 114374: extended pcr_nonce from 32-bit to 256-bit
Merged PR 114111: added sha256 and hmac cov
Merged PR 113936: Promote Pipeline - TRNG L0 regression speedup
Merged PR 113911: UVM regression timeout increase
Merged PR 113388: added hmac smoke_test and update sha params
Merged PR 113659: Promote pipeline runtime optimizations
Merged PR 113010: RAS test for non fatal errors, WDT checks
Merged PR 113246: SOC_IFC - Fix for HW ERROR registers with bad rsvd fields
Merged PR 113052: New UVM mailbox test cases - inject random delays
Merged PR 113151: Fix for mbox sequence base
Merged PR 113035: SHA512 Coverage

Related work items: #490148

Retry dlen-read if invalid PAUSER causes access error Resolves a regression failure 6/21/2023 Related work items: #490462

Add test sequences that inject random delays in mailbox flows. Also add a fix for the mbox_dataout prediction logic that initializes the register to 0 on every mailbox flow (as is done in hw) to account for the case where no data is written to the mailbox during the command initialize phase (e.g. DLEN = 0). Related work items: #442947, #490264

…fields Remove 'rsvd' fields with bad access privileges from HW ERROR regs; regenerate RDL. Add a promote pipeline check to enforce RDL file generation. Fix the randomization seed in soc_ifc_tb reg test. Related work items: #485424

- RAS smoke test changes to include non fatal errors + related TB changes - WDT SVAs to check timer reset conditions - Enable clock gating tests in L0 regression and exclude from Verilator regression Related work items: #296045, #470609, #470611, #470613, #470616, #470619, #470623, #471935, #483518, #490558

Modify promote pipeline jobs to improve run-time: - RDL file check is only run if any ".rdl" file or any RDL template file is modified relative to the 'master' branch - File list generation and check job are only run if any 'compile.yml' is modified relative to the 'master' branch - Verilator regression is run by spawning each smoke test as a separate run thread to parallelize the regression Related work items: #494085

added hmac smoke_test and update sha params Related work items: #490621, #490622, #490629

Increase run timeout from 2hr (default) to 12 hours for longer tests Resolves the single timeout test from [this regression](https://dev.azure.com/ms-tsd/AHA_POC/_apps/hub/MSFTCPSDevOps.metadata-search-page.triage#/regressions/1644878/tests/423071070) Related work items: #498281

Improve runtime by submitting TRNG L0 regression in parallel with regular L0 regression, and reduce the test list Related work items: #500117

added sha256 cov added hmac cov added more tests for sha512 cov Related work items: #494324, #494326

Related work items: #510605

… interrupt block registers Specialized tests for RV_MTIME registers, INTR_BLOCK_RF registers for both soc_ifc and sha512_acc blocks. Some test environment cleanup. Related work items: #422658, #448196, #470603

…check Change register check approach to avoid an edge case where new dlen/cmd = old dlen/cmd and flags false error Related work items: #511911

Old-school file-copy merge from dev-msft (GitHub repository) into internal to resolve diffs. Includes: * tool updates (from latest caliptra_config) to GCC 11.2.0, Verilator 5.012, Verdi 2021.09-1 * prim rename to caliptra_prim * assorted verilator flow updates * QSPI/TRNG/UART all enabled Related work items: #510715, #510720

* New mbox sequence with data size exceeding mbox capacity * Enhance the interference/contention sequence to inject random AHB register reads during the mailbox flow Includes bug fixes in mailbox for data corruption issues on invalid DLEN test case. Related work items: #422631, #442941, #442943, #442945, #503635, #510161

…g fixes, coverage updates Includes: 1. Mailbox flow fsm updates in testbench 2. Mailbox flow + clock gating test (halts core at multiple points throughout the test) 3. DOE + clock gating test 4. DOE + scan/debug mode test 5. RTL updates to block writes to KV during scan/debug modes, zeroize crypto regs during scan/debug modes 6. RDL update to add hwclr for DOE_IV reg 7. DOE SVA fixes 8. KV/PV coverage fixes + new sequence Related work items: #480553, #483504, #510614, #510617, #510620, #511132, #511840, #512220

… fw update reset Clocks are disabled just before warm reset is asserted to prevent RDC on flops not reset (powergood). Masking uC outputs (AHB bus forced idle) just before fw update reset flow asserts uc reset. Various signals throughout moved to appropriate noncore reset signal. Gated clock used more places for RDC purposes. New gated clock just for RDC. PCR locks reset on uc reset like KV. Related work items: #470220, #512682

calebofearth · 2023-07-11T01:10:11Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

howardtr · 2023-07-11T16:23:22Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

@calebofearth - for my own understanding, could you elaborate on this?

calebofearth · 2023-07-11T16:40:20Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

@calebofearth - for my own understanding, could you elaborate on this?

Hi @howardtr , it's related to the issues discussed in #126. There are some new smoke tests being brought in from our internal repo that will exercise the same bug in Verilator and cause the workflow to break.
All we really need to do is modify caliptra-rtl/.github/workflows/build-test-verilator.yml at dev-msft · chipsalliance/caliptra-rtl · GitHub to add them to the exclude list.

howardtr · 2023-07-11T16:46:32Z

src/integration/rtl/caliptra_top.sv

@@ -541,13 +546,18 @@ el2_veer_wrapper rvtop (
 // SB and LSU AHB master mux
 ahb_lite_2to1_mux #(
 .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),
+<<<<<<< HEAD


Looks like there's a merge issue here

Thanks, I've pushed a fix now.

howardtr · 2023-07-11T16:47:38Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

@calebofearth - for my own understanding, could you elaborate on this?

Hi @howardtr , it's related to the issues discussed in #126. There are some new smoke tests being brought in from our internal repo that will exercise the same bug in Verilator and cause the workflow to break. All we really need to do is modify caliptra-rtl/.github/workflows/build-test-verilator.yml at dev-msft · chipsalliance/caliptra-rtl · GitHub to add them to the exclude list.

Sg!

anjpar · 2023-07-11T17:07:50Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

@calebofearth - for my own understanding, could you elaborate on this?

Hi @howardtr , it's related to the issues discussed in #126. There are some new smoke tests being brought in from our internal repo that will exercise the same bug in Verilator and cause the workflow to break. All we really need to do is modify caliptra-rtl/.github/workflows/build-test-verilator.yml at dev-msft · chipsalliance/caliptra-rtl · GitHub to add them to the exclude list.

Exclude list updated in dev-msft branch with additional tests that needed to be excluded.

anjpar · 2023-07-11T17:08:48Z

@upadhyayulakiran has some smoke test exclusions to add for the verilator check, which will be necessary for the Verilator workflow to pass.

Exclude list has been updated!

bharatpillilli · 2023-07-11T19:30:06Z

@mkurc-ant - Seemingly higher verilator version is not hitting the same issue. It is an issue though that we will have to address nevertheless. We need this bug to be filed on verilator too.

For now, we may be moving the verilator to higher version (@calebofearth is checking on this), file an internal bug on the casez/default statement to check why it was removed by @Nitsirks for RDC fixes and PR this one.

We can tackle the default one as a separate PR to see if Avirup is hitting any RDC issues with casez and default.

calebofearth · 2023-07-11T19:39:25Z

@mkurc-ant - Seemingly higher verilator version is not hitting the same issue. It is an issue though that we will have to address nevertheless. We need this bug to be filed on verilator too.

For now, we may be moving the verilator to higher version (@calebofearth is checking on this), file an internal bug on the casez/default statement to check why it was removed by @Nitsirks for RDC fixes and PR this one.

We can tackle the default one as a separate PR to see if Avirup is hitting any RDC issues with casez and default.

Just for a little more context on this comment:
Verilator 5.002 throws a warning about the unique casez having incomplete coverage in soc_ifc_boot_fsm.sv, as seen in the interactive debugger Workflow
Verilator 5.012, as seen in the Verilator smoke test workflow, does not throw the same error.

calebofearth · 2023-07-11T23:49:11Z

In order to get the workflows passing, we need to update the 'interactive debugger' verilator version to 5.012.
I believe that just means updating line 21 in interactive-debugging.yml.
We should file two separate bugs related to the unique casez warning that was fired:

Bug against caliptra-rtl about soc_ifc_boot_fsm to clean up the case statement
Bug against Verilator 5.012 not providing this warning, which would be a legitimate warning message"

mojtaba-bisheh and others added 17 commits July 10, 2023 16:03

Merged PR 113035: SHA512 Coverage

5f942ae

Related work items: #490148

Merged PR 113151: Fix for mbox sequence base

0b798a3

Retry dlen-read if invalid PAUSER causes access error Resolves a regression failure 6/21/2023 Related work items: #490462

Merged PR 113388: added hmac smoke_test and update sha params

d87f440

added hmac smoke_test and update sha params Related work items: #490621, #490622, #490629

Merged PR 113936: Promote Pipeline - TRNG L0 regression speedup

c090115

Improve runtime by submitting TRNG L0 regression in parallel with regular L0 regression, and reduce the test list Related work items: #500117

Merged PR 114111: added sha256 and hmac cov

f8b74c3

added sha256 cov added hmac cov added more tests for sha512 cov Related work items: #494324, #494326

Merged PR 114374: extended pcr_nonce from 32-bit to 256-bit

e462988

Related work items: #510605

Merged PR 114587: New soc_ifc register tests, special cases including…

0d9b13d

… interrupt block registers Specialized tests for RV_MTIME registers, INTR_BLOCK_RF registers for both soc_ifc and sha512_acc blocks. Some test environment cleanup. Related work items: #422658, #448196, #470603

Merged PR 114881: UVM mailbox sequence fix for invalid PAUSER access …

ce475e3

…check Change register check approach to avoid an edge case where new dlen/cmd = old dlen/cmd and flags false error Related work items: #511911

anjpar requested review from calebofearth, howardtr and bharatpillilli July 11, 2023 00:47

bharatpillilli approved these changes Jul 11, 2023

View reviewed changes

howardtr requested changes Jul 11, 2023

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resolved merge conflict

b5e5bfc

howardtr approved these changes Jul 11, 2023

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This was referenced Jul 11, 2023

PCR quoting nonce is too small #139

Closed

Timing path from PSEL to PRDATA #137

Closed

Combinatorial loop in ahb lite signals #122

Closed

Caliptra RDC violations #89

Closed

Update verilator version to 5.012

245c078

This was referenced Jul 11, 2023

Boot FSM case statement incomplete #150

Closed

Warning message for CASEINCOMPLETE generated in 5.002 does not occur in 5.012 verilator/verilator#4357

Open

calebofearth approved these changes Jul 12, 2023

View reviewed changes

anjpar merged commit f71a9aa into dev-msft Jul 12, 2023
42 checks passed

anjpar deleted the dev-msft-20230710 branch July 12, 2023 15:51

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Dev msft 20230710 #149

Dev msft 20230710 #149

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Dev msft 20230710 #149

Dev msft 20230710 #149

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