[DNM] soc: arm: cypress: psoc6: Introduce pinctrl #28645
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| /* | ||
| * Copyright (c) 2020 Linaro Limited | ||
| * Copyright (c) 2020 ATL Electronics | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #ifndef PINCTRL_CYPRESS_PSOC6_H_ | ||
| #define PINCTRL_CYPRESS_PSOC6_H_ | ||
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| #include <sys/util_macro.h> | ||
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| /** | ||
| * Functions are defined using HSIOM SEL | ||
| */ | ||
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| #define HSIOM_SEL_gpio 0 | ||
| #define HSIOM_SEL_gpio_dsi 1 | ||
| #define HSIOM_SEL_dsi_dsi 2 | ||
| #define HSIOM_SEL_dsi_gpio 3 | ||
| #define HSIOM_SEL_amuxa 4 | ||
| #define HSIOM_SEL_amuxb 5 | ||
| #define HSIOM_SEL_amuxa_dsi 6 | ||
| #define HSIOM_SEL_amuxb_dsi 7 | ||
| #define HSIOM_SEL_act_0 8 | ||
| #define HSIOM_SEL_act_1 9 | ||
| #define HSIOM_SEL_act_2 10 | ||
| #define HSIOM_SEL_act_3 11 | ||
| #define HSIOM_SEL_ds_0 12 | ||
| #define HSIOM_SEL_ds_1 13 | ||
| #define HSIOM_SEL_ds_2 14 | ||
| #define HSIOM_SEL_ds_3 15 | ||
| #define HSIOM_SEL_act_4 16 | ||
| #define HSIOM_SEL_act_5 17 | ||
| #define HSIOM_SEL_act_6 18 | ||
| #define HSIOM_SEL_act_7 19 | ||
| #define HSIOM_SEL_act_8 20 | ||
| #define HSIOM_SEL_act_9 21 | ||
| #define HSIOM_SEL_act_10 22 | ||
| #define HSIOM_SEL_act_11 23 | ||
| #define HSIOM_SEL_act_12 24 | ||
| #define HSIOM_SEL_act_13 25 | ||
| #define HSIOM_SEL_act_14 26 | ||
| #define HSIOM_SEL_act_15 27 | ||
| #define HSIOM_SEL_ds_4 28 | ||
| #define HSIOM_SEL_ds_5 29 | ||
| #define HSIOM_SEL_ds_6 30 | ||
| #define HSIOM_SEL_ds_7 31 | ||
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| /* Create a pincfg device tree node: | ||
| * | ||
| * The node name and nodelabel will be of the form: | ||
| * | ||
| * NODE = p<port>_<pin>_<inst>_<signal> | ||
| * | ||
| * NODE: NODE { | ||
| * cypress,pins = < &p<port> <port> <pin> HSIOM_SEL_<hsiom> >; | ||
| * flags_1; | ||
| * ... | ||
| * flags_N; | ||
| * } | ||
| * | ||
| * So for example: | ||
| * | ||
| * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6); | ||
| * | ||
| * Will become: | ||
| * | ||
| * p5_0_uart5_rx: p5_0_uart5_rx { | ||
| * cypress,pins = <&p5 0x5 0x0 0x12 >; | ||
| * } | ||
| * | ||
| * Flags are optional and should be pass one by one as arguments: | ||
| * | ||
| * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6, bias-pull-up, input-enable); | ||
| * | ||
| * Will become: | ||
| * | ||
| * p5_0_uart5_rx: p5_0_uart5_rx { | ||
| * cypress,pins = <&p5 0x5 0x0 0x12 >; | ||
| * bias-pull-up; | ||
| * input-enable; | ||
| * } | ||
| * | ||
| * For the complete list of flags see cypress,psoc6-pinctrl.yaml | ||
| * | ||
| */ | ||
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| #define DT_CYPRESS_HSIOM_FLAG(flag) flag; | ||
| #define DT_CYPRESS_HSIOM_FLAGS(...) \ | ||
| MACRO_MAP_CAT(DT_CYPRESS_HSIOM_FLAG __VA_OPT__(,) __VA_ARGS__) | ||
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| #define DT_CYPRESS_HSIOM(inst, signal, port, pin, hsiom, ...) \ | ||
| p##port##_##pin##_##inst##_##signal: \ | ||
| p##port##_##pin##_##inst##_##signal { \ | ||
| cypress,pins = < &p##port port pin HSIOM_SEL_##hsiom > ; \ | ||
| DT_CYPRESS_HSIOM_FLAGS(__VA_ARGS__) \ | ||
| } | ||
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| #endif /* PINCTRL_CYPRESS_PSOC6_H_ */ | ||
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| /* | ||
| * Copyright (c) 2020 ATL Electronics | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #include "pinctrl_cypress_psoc6.h" | ||
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| / { | ||
| soc { | ||
| pinctrl@40310000 { | ||
| /* instance, signal, port, pin, hsiom [, flag1, ... ] */ | ||
| DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, input-enable); | ||
| DT_CYPRESS_HSIOM(uart5, tx, 5, 1, act_6, drive-push-pull); | ||
| DT_CYPRESS_HSIOM(uart6, rx, 13, 0, act_6, input-enable); | ||
| DT_CYPRESS_HSIOM(uart6, tx, 13, 1, act_6, drive-push-pull); | ||
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There was a problem hiding this comment. I'm not familiar with this SoC, but if the number of pinctrl options is large, you may consider making pinctrl part of the SoC HAL as we've done for ST. There was a problem hiding this comment. I don't have intention to move this to HAL and mix Zephyr with Cypress. There was a problem hiding this comment. It doesn't have to be in PDL directly. It could be inside a dts/ at cypress module root. |
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| }; | ||
| }; | ||
| }; | ||
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| Original file line number | Diff line number | Diff line change |
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| # Copyright (c) 2020 ATL Electronics | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| description: Cypress GPIO PORT node | ||
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| compatible: "cypress,psoc6-gpio" | ||
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| include: [gpio-controller.yaml, base.yaml] | ||
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| properties: | ||
| reg: | ||
| required: true | ||
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| interrupts: | ||
| required: true | ||
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| label: | ||
| required: true | ||
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| "#gpio-cells": | ||
| const: 2 | ||
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| "#cypress,pin-cells": | ||
| type: int | ||
| required: true | ||
| const: 3 | ||
| description: Number of items to expect in a cypress,pins specifier | ||
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| gpio-cells: | ||
| - pin | ||
| - flags | ||
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| cypress,pin-cells: | ||
| - port | ||
| - pin | ||
| - hsiom | ||
|
There was a problem hiding this comment. Why does this commit introduce gpio bindings? Shouldn't it be pinctrl stuff only? I think it's better to split gpio and pinctrl stuff, they are in principle orthogonal things. |
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| # Copyright (c) 2020 ATL Electronics | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| description: Cypress High Speed I/O Matrix | ||
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| compatible: "cypress,psoc6-hsiom" | ||
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| include: base.yaml | ||
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| properties: | ||
| reg: | ||
| required: true | ||
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| interrupts: | ||
| required: true | ||
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| label: | ||
| required: true |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,11 @@ | ||
| # Copyright (c) 2020 ATL Electronics | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| properties: | ||
| map-nvic: | ||
| type: int | ||
| required: false | ||
| description: | | ||
| Cortex-M0+ NVIC user defined interrupt line. The PSoC-6 SoC needs that | ||
| user select which interrupts Cortex-M0+ will handle and this map the | ||
| peripheral interrupt to be bind at driver initialization. |
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I wonder if pin information can be encoded into an uint32, similar to what we do on STM32: https:/zephyrproject-rtos/zephyr/blob/master/include/dt-bindings/pinctrl/stm32-pinctrl.h#L42
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I think it already is at end:
This is the structure that will handle:
The soc/arm/cypress/common/cypress_psoc6_dt.h have a macro CY_PSOC6_DT_PIN that will collect from DT and create above structure at driver level at build time.
The DT_CYPRESS_HSIOM is a variable length argument list that accept flags:
First 5 parameters are mandatory, than flags are added one by one with commas.
DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6);
DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, bias-pull-up);
DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, bias-pull-up, input-enable [, etc]);
Above all entries are valid and create a node like:
The CY_PSOC6_DT_PIN will combine 0x12 (function) + bias-pull-up + input-enable as flags. From &p5 we get reg addr and 0x0 is the pin itself at p5. The remaining 0x5 is the uart instance number and doesn't have nothing to do with pinctrl and probably will be dropped. It was necessary to solve the chicken and egg problem when platform doesn't have nothing.