Caliptra RDC violations

[amullick007]

The RDC analysis and violations have been summarized at Caliptra_RDC_Analysis.pdf

The detailed list of all paths are attached in the excel file at RDC_Violations.xlsx

Final decision/conclusion to prevent RDC crossing are summarized as below:-

• Move BootFSM to pwrgood domain
• BootFSM should look at firmware reset assertion and cptra_rst_b assertion to generate an assert_window signal which will be used to gate the clocks of the destination flops
• assert_window from BootFSM will be fed to caliptra_top.cg.caliptra_icg to gate caliptra_top.clk_cg
• A new ICG needs to be added for caliptra_top.rvtop.clk whose gating will be controlled by assert_window from BootFSM
• Since cptra_rst_b is going to be used by BootFSM, we should move the reset of the flops which are currently on cptra_rst_b to cptra_noncore_rst_b
• BootFSM should delay the assertion of warm reset to ensure that the clock is gated before the assertion edge

In addition to the above, please check the issue listed in Section 6 related to the logic driving dbg_dm_rst_l in Caliptra_RDC_Analysis.pdf

Local RTL changes done at my end are present at https:/amullick40412/caliptra-rtl/commit/bef0ef2a9bd894565cdbb5d30443bf37f79f54cf

[bharatpillilli]

Fixes WIP and then we will have more back & forth clean up

[bharatpillilli]

@Nitsirks - plz let @amullick40412 know when the changes are ready so that he can do his run/clean up

[Nitsirks]

@amullick40412 Working out a few kinks in the implementation, I expect to have a branch out tonight

[Nitsirks]

I have pushed a branch with my WIP so far. I think we should see most of the issues cleared up and want to confirm that.

There are still some bugs/concerns that need ironed out.

https:/chipsalliance/caliptra-rtl/tree/michnorris-msft-issue89

[bharatpillilli]

#149 sync to dev-msft should fix non-debug paths of this. Avirup will run RDC to check on it once the sync is complete.